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Accumulator

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Jun 27th, 2018
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  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3. use ieee.std_logic_arith.all;
  4.  
  5. entity accumulator is
  6. port(
  7.     clk: in std_logic;
  8.     reset: in std_logic;
  9.     input1: in std_logic;
  10.     input2: in std_logic;
  11.     output: out std_logic
  12. );
  13. end accumulator;
  14.  
  15. architecture arch of accumulator is
  16.  
  17. signal reg: std_logic; -- register
  18. signal and_gate: std_logic; -- to make the code clearer
  19.  
  20. begin
  21.  
  22. process(clk)
  23.     begin
  24.     if(rising_edge(clk)) then
  25.         if(reset = '1') then
  26.             reg <= '0';
  27.         else
  28.             reg <= and_gate XOR reg;
  29.         end if;
  30.     end if;
  31. end process;
  32.  
  33. and_gate <= input1 AND input2;
  34. output <= and_gate XOR reg;
  35.  
  36. end arch;
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