process(clk, rst)
    variable xored : std_logic_vector(15 downto 0);
    begin
        if(rst = '1') then
            state <= load;
            seed  <= load;
        elsif(rising_edge(clk)) then
            if(state(0) = '1') then
                xored := state xor x"B400";
            end if;
            xored(15 - 1 downto 0) := xored(15 downto 0 + 1);
            state <= xored;
        end if;
    end process;