SR FLIP-FLOP ASYNC

-- design.vhd

library IEEE;
use IEEE.std_logic_1164.all;

 entity sr is
    port(S, R : in std_logic;
         Q, Qn : out std_logic);
 end entity;

 architecture sr_arch of sr is
    begin
        process(S, R)
        begin
            if(S = '0' and R = '0') then
                Q <= Q;
                Qn <= Qn;
            elsif(S = '0' and R = '1') then
                Q <= '0';
                Qn <= '1';
            elsif(S = '1' and R = '0') then
                Q <= '1';
                Qn <= '0';
            elsif(S = '1' and R = '1') then
                Q <= '0';
                Qn <= '0';
            end if;
        end process;
end architecture sr_arch;

-- testbench.vhd

library IEEE;
use IEEE.std_logic_1164.all;

entity sr_tb is
end entity;

architecture sr_tb_arch of sr_tb is
    signal S, R, Q, Qn : std_logic;

    begin
        DUT1 : entity work.sr(sr_arch)
               port map(S, R, Q, Qn);

        STIMULUS : process
        begin
            S <= '0'; R <= '0';
            wait for 10ns;
            S <= '0'; R <= '1';
            wait for 10ns;
            S <= '1'; R <= '0';
            wait for 10ns;
            S <= '1'; R <= '1';
            wait for 10ns;
            S <= 'X'; R <= 'X';
            wait for 10ns;
        end process;
end architecture sr_tb_arch;