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VGA_Moving_Square

Dec 5th, 2014
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VHDL 4.37 KB | None | 0 0
  1.  ----------------------------------------------------------------------------------
  2.  -- Company:
  3.  -- Engineer:
  4.  --
  5.  -- Create Date:    09:55:25 11/21/2014
  6.  -- Design Name:
  7.  -- Module Name:    Counter - Behavioral
  8.  -- Project Name:
  9.  -- Target Devices:
  10.  -- Tool versions:
  11.  -- Description:
  12.  --
  13.  -- Dependencies:
  14.  --
  15.  -- Revision:
  16.  -- Revision 0.01 - File Created
  17.  -- Additional Comments:
  18.  --
  19.  ----------------------------------------------------------------------------------
  20.  library IEEE;
  21.  use IEEE.STD_LOGIC_1164.ALL;
  22.  use ieee.std_logic_unsigned.all;
  23.  
  24.  -- Uncomment the following library declaration if using
  25.  -- arithmetic functions with Signed or Unsigned values
  26.  use IEEE.NUMERIC_STD.ALL;
  27.  
  28.  -- Uncomment the following library declaration if instantiating
  29.  -- any Xilinx primitives in this code.
  30.  --library UNISIM;
  31.  --use UNISIM.VComponents.all;
  32.  
  33.  entity VGADriver is
  34.       Port ( Reset : in  STD_LOGIC;
  35.                 CLK50 : in  STD_LOGIC;
  36.                 Up, Left, Down, Right : in STD_LOGIC;
  37.                 R, G, B, Hsync, Vsync : out STD_LOGIC);
  38.  end VGADriver;
  39.  
  40.  architecture Behavioral of VGADriver is
  41.  
  42.  signal Add1, Add2 : STD_LOGIC_VECTOR(9 downto 0);
  43.  signal Reg1, Reg2 : STD_LOGIC_VECTOR(9 downto 0);
  44.  signal Mux1, Mux2 : STD_LOGIC_VECTOR(9 downto 0);
  45.  signal Cmp1, Cmp2 : STD_LOGIC;
  46.  
  47.  signal Rows : STD_LOGIC_VECTOR(9 downto 0) := "1100100000";
  48.  signal Columns : STD_LOGIC_VECTOR(9 downto 0) := "1000001001";
  49.  
  50.  signal CLK : STD_LOGIC;
  51.  
  52.  ----------------------------
  53.  signal PosX, RegX : STD_LOGIC_VECTOR(9 downto 0) := "0010010000";
  54.  signal PosY, RegY : STD_LOGIC_VECTOR(9 downto 0) := "0000011111";
  55.  
  56.  signal AddX, SubX : STD_LOGIC_VECTOR(9 downto 0);
  57.  signal AddY, SubY : STD_LOGIC_VECTOR(9 downto 0);
  58.  ----------------------------
  59.  signal TimerReg, TimerAdd, TimerMux : STD_LOGIC_VECTOR(25 downto 0);
  60.  signal TimerCmp : STD_LOGIC;
  61.  
  62.  begin
  63.  
  64.  
  65. --posX <= posX + 1 when Right = '1' else posX - 1 when Left = '1';
  66. --posY <= posY + 1 when Down = '1'  else posY - 1 when Up = '1';
  67.  
  68. CLK <= not(CLK) when rising_edge(CLK50);
  69.  
  70. Hsync <= '0' when 0 <= Reg1 and Reg1 < 96 else '1';
  71.  
  72. Vsync <= '0' when 0 <= Reg2 and Reg2 < 2 else '1';
  73.  
  74. R <= '0' when (0 <= Reg1 and Reg1 < 144) OR (144+640 <= Reg1 and Reg1 < 144+640+16) OR (0 <= Reg2 and Reg2 < 31) OR (31+480 <= Reg2 and Reg2 < 31+480+10);
  75. B <= '0' when (0 <= Reg1 and Reg1 < 144) OR (144+640 <= Reg1 and Reg1 < 144+640+16) OR (0 <= Reg2 and Reg2 < 31) OR (31+480 <= Reg2 and Reg2 < 31+480+10);
  76. G <= '0' when (0 <= Reg1 and Reg1 < 144) OR (144+640 <= Reg1 and Reg1 < 144+640+16) OR (0 <= Reg2 and Reg2 < 31) OR (31+480 <= Reg2 and Reg2 < 31+480+10) else
  77.         '1' when (PosX <= Reg1 and Reg1 < PosX+16) and (PosY <= Reg2 and Reg2 < PosY+16) else
  78.         '0';
  79.                                        
  80.  
  81. ----------------------------------------
  82.  
  83.  Add1 <= Reg1 + "0000000001";
  84.  
  85.  Mux1 <= Add1 when Cmp1 = '0' else "0000000000" when Cmp1 = '1';
  86.  
  87.  Cmp1 <= '1' when Add1 > Rows else '0';
  88.  
  89.  Reg1 <= "0000000000" when Reset = '0' else Mux1 when rising_edge(CLK);
  90.  
  91. -----------------------------------------
  92.  
  93.  Add2 <= Reg2 + "0000000001";
  94.  
  95.  Mux2 <= "0000000000" when Cmp2 = '1' and Cmp1='1' else
  96.          Add2 when Cmp2 = '0' and Cmp1 = '1' else
  97.             Reg2;
  98.  
  99.  Cmp2 <= '1' when Add2 > Columns else '0';
  100.  
  101.  Reg2 <= "0000000000" when Reset = '0' else Mux2 when rising_edge(CLK);
  102.  
  103. -----------------------------------------
  104. -- Timer
  105.                        
  106. TimerAdd <= TimerReg + "00000000000000000000000001";
  107. TimerReg <= TimerMux when rising_edge(CLK);
  108. TimerMux <= "00000000000000000000000000" when TimerCmp = '1' else
  109.                 TimerAdd ;
  110. TimerCmp <= '1' when TimerAdd > "00000001111010000100100000" else '0';
  111.  
  112. -----------------------------------------
  113. -- PosX
  114.  
  115. RegX <= PosX when rising_edge(CLK) ;
  116.  
  117. AddX <= RegX + "0000000001";
  118. SubX <= RegX - "0000000001";
  119.  
  120. PosX <= AddX when (Right = '1' and TimerCmp = '1' and RegX < "1100000000") else
  121.           SubX when (Right = '0' and TimerCmp = '1' and RegX > "0010010000") else
  122.           "0010010000" when Reset = '0' else
  123.           RegX;
  124.          
  125. -----------------------------------------
  126. -- PosY
  127.  
  128. RegY <= PosY when rising_edge(CLK) ;
  129.  
  130. AddY <= RegY + "0000000001";
  131. SubY <= RegY - "0000000001";
  132.  
  133. PosY <= AddY when (Down = '1' and TimerCmp = '1' and RegY < "0111111001") else
  134.           SubY when (Down = '0' and TimerCmp = '1' and RegY > "0000011111") else
  135.           "0010010000" when Reset = '0' else
  136.           RegY;
  137.          
  138.          
  139.  
  140.  
  141.  end Behavioral;
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