Advertisement
Not a member of Pastebin yet?
Sign Up,
it unlocks many cool features!
- ----------------------------------------------------------------------------------
- -- Company:
- -- Engineer:
- --
- -- Create Date: 09:55:25 11/21/2014
- -- Design Name:
- -- Module Name: Counter - Behavioral
- -- Project Name:
- -- Target Devices:
- -- Tool versions:
- -- Description:
- --
- -- Dependencies:
- --
- -- Revision:
- -- Revision 0.01 - File Created
- -- Additional Comments:
- --
- ----------------------------------------------------------------------------------
- library IEEE;
- use IEEE.STD_LOGIC_1164.ALL;
- use ieee.std_logic_unsigned.all;
- -- Uncomment the following library declaration if using
- -- arithmetic functions with Signed or Unsigned values
- use IEEE.NUMERIC_STD.ALL;
- -- Uncomment the following library declaration if instantiating
- -- any Xilinx primitives in this code.
- --library UNISIM;
- --use UNISIM.VComponents.all;
- entity VGADriver is
- Port ( Reset : in STD_LOGIC;
- CLK50 : in STD_LOGIC;
- Up, Left, Down, Right : in STD_LOGIC;
- R, G, B, Hsync, Vsync : out STD_LOGIC);
- end VGADriver;
- architecture Behavioral of VGADriver is
- signal Add1, Add2 : STD_LOGIC_VECTOR(9 downto 0);
- signal Reg1, Reg2 : STD_LOGIC_VECTOR(9 downto 0);
- signal Mux1, Mux2 : STD_LOGIC_VECTOR(9 downto 0);
- signal Cmp1, Cmp2 : STD_LOGIC;
- signal Rows : STD_LOGIC_VECTOR(9 downto 0) := "1100100000";
- signal Columns : STD_LOGIC_VECTOR(9 downto 0) := "1000001001";
- signal CLK : STD_LOGIC;
- ----------------------------
- signal PosX, RegX : STD_LOGIC_VECTOR(9 downto 0) := "0010010000";
- signal PosY, RegY : STD_LOGIC_VECTOR(9 downto 0) := "0000011111";
- signal AddX, SubX : STD_LOGIC_VECTOR(9 downto 0);
- signal AddY, SubY : STD_LOGIC_VECTOR(9 downto 0);
- ----------------------------
- signal TimerReg, TimerAdd, TimerMux : STD_LOGIC_VECTOR(25 downto 0);
- signal TimerCmp : STD_LOGIC;
- begin
- --posX <= posX + 1 when Right = '1' else posX - 1 when Left = '1';
- --posY <= posY + 1 when Down = '1' else posY - 1 when Up = '1';
- CLK <= not(CLK) when rising_edge(CLK50);
- Hsync <= '0' when 0 <= Reg1 and Reg1 < 96 else '1';
- Vsync <= '0' when 0 <= Reg2 and Reg2 < 2 else '1';
- R <= '0' when (0 <= Reg1 and Reg1 < 144) OR (144+640 <= Reg1 and Reg1 < 144+640+16) OR (0 <= Reg2 and Reg2 < 31) OR (31+480 <= Reg2 and Reg2 < 31+480+10);
- B <= '0' when (0 <= Reg1 and Reg1 < 144) OR (144+640 <= Reg1 and Reg1 < 144+640+16) OR (0 <= Reg2 and Reg2 < 31) OR (31+480 <= Reg2 and Reg2 < 31+480+10);
- G <= '0' when (0 <= Reg1 and Reg1 < 144) OR (144+640 <= Reg1 and Reg1 < 144+640+16) OR (0 <= Reg2 and Reg2 < 31) OR (31+480 <= Reg2 and Reg2 < 31+480+10) else
- '1' when (PosX <= Reg1 and Reg1 < PosX+16) and (PosY <= Reg2 and Reg2 < PosY+16) else
- '0';
- ----------------------------------------
- Add1 <= Reg1 + "0000000001";
- Mux1 <= Add1 when Cmp1 = '0' else "0000000000" when Cmp1 = '1';
- Cmp1 <= '1' when Add1 > Rows else '0';
- Reg1 <= "0000000000" when Reset = '0' else Mux1 when rising_edge(CLK);
- -----------------------------------------
- Add2 <= Reg2 + "0000000001";
- Mux2 <= "0000000000" when Cmp2 = '1' and Cmp1='1' else
- Add2 when Cmp2 = '0' and Cmp1 = '1' else
- Reg2;
- Cmp2 <= '1' when Add2 > Columns else '0';
- Reg2 <= "0000000000" when Reset = '0' else Mux2 when rising_edge(CLK);
- -----------------------------------------
- -- Timer
- TimerAdd <= TimerReg + "00000000000000000000000001";
- TimerReg <= TimerMux when rising_edge(CLK);
- TimerMux <= "00000000000000000000000000" when TimerCmp = '1' else
- TimerAdd ;
- TimerCmp <= '1' when TimerAdd > "00000001111010000100100000" else '0';
- -----------------------------------------
- -- PosX
- RegX <= PosX when rising_edge(CLK) ;
- AddX <= RegX + "0000000001";
- SubX <= RegX - "0000000001";
- PosX <= AddX when (Right = '1' and TimerCmp = '1' and RegX < "1100000000") else
- SubX when (Right = '0' and TimerCmp = '1' and RegX > "0010010000") else
- "0010010000" when Reset = '0' else
- RegX;
- -----------------------------------------
- -- PosY
- RegY <= PosY when rising_edge(CLK) ;
- AddY <= RegY + "0000000001";
- SubY <= RegY - "0000000001";
- PosY <= AddY when (Down = '1' and TimerCmp = '1' and RegY < "0111111001") else
- SubY when (Down = '0' and TimerCmp = '1' and RegY > "0000011111") else
- "0010010000" when Reset = '0' else
- RegY;
- end Behavioral;
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement