library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity cw0 is
port
(
    a   :   in std_logic_vector(4 downto 0);
    f2  : out std_logic

);
end entity;

architecture funkcja0 of cw0 is
begin


    process(a)
    begin
        case(to_integer(unsigned(a(2 downto 0)))) is
        when 0 => f2 <= not a(4);
        when 1 => f2 <= '-';
        when 2 => f2 <= a(4);
        when 3 => f2 <= not a(4);
        when 4 => f2 <= not a(4);
        when 5 => f2 <= a(3);
        when 6 => f2 <= not a(4);
        when 7 => f2 <= a(4);
        when others => f2 <= '-';
        end case;
    end process;

end architecture;