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May 16th, 2018
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VHDL 0.88 KB | None | 0 0
  1. procedure syncGenerator(signal syncCounter : inout integer range 0 to 1023;
  2.                                     signal syncOut,blank : out std_logic;
  3.                                     constant frontPorch,backPorch,dataLen,syncWidth: in natural) is
  4.     begin
  5.         --If syncCounter is less than max--
  6.         if(syncCounter < (frontPorch + backPorch + dataLen + syncWidth)) then
  7.             --Increment--
  8.             syncCounter <= (syncCounter + 1);
  9.             --If syncCounter is less than max - syncWidth--
  10.             if(syncCounter<(frontPorch + backPorch + dataLen)) then
  11.                 --SyncOut is high--
  12.                 syncOut <= '1';
  13.             else
  14.                 syncOut <= '0';
  15.             end if;
  16.             --If syncCounter is greater than backPorch and less than backPorch + dataLen--
  17.             if ((syncCounter > backPorch) and (syncCounter<(backPorch + dataLen))) then
  18.                 --Blank out is 0--
  19.                 blank <= '0';
  20.             else
  21.                 blank <= '1';
  22.             end if;
  23.         --Else reset counter
  24.         else
  25.             syncCounter <= 0;
  26.         end if;
  27.     end syncGenerator;
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