VHDL - Number detection

--- Author: Matej Arlović, 2018.
--- Ponašajni numdet_and1:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity numdet_and1 is
    port(
            A : in STD_LOGIC;
            B : in STD_LOGIC;
            C : in STD_LOGIC;
            Y : out STD_LOGIC
        );
end numdet_and1;

architecture Behavioral of numdet_and1 is

begin
    Y <= A and B and C;
end Behavioral;

--- Ponašajni numdet_or1:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity numdet_or1 is
    port(
        A: in STD_LOGIC;
        B: in STD_LOGIC;
        C: in STD_LOGIC;
        Y: out STD_LOGIC
    );
end numdet_or1;

architecture Behavioral of numdet_or1 is

begin
    Y <= A or B or C;
end Behavioral;

--- Strukturni numdet:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity numdet is
    port(
        A, B, C: in STD_LOGIC;
        Y: out STD_LOGIC
    );
end numdet;

architecture Strukturni of numdet is

signal E, F, G: STD_LOGIC;

begin
    L1: entity work.numdet_and1 port map(A, not(B), C, E);
    L2: entity work.numdet_and1 port map(A, B, not(C), F);
    L3: entity work.numdet_and1 port map(A, B, C, G);
    L4: entity work.numdet_or1 port map(A=>E, B=>F, C=>G, Y=>Y);
end Strukturni;

--- Testbench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY numdet_w IS
END numdet_w;

ARCHITECTURE behavior OF numdet_w IS
    COMPONENT numdet
    PORT(
         A : IN  std_logic;
         B : IN  std_logic;
         C : IN  std_logic;
         Y : OUT  std_logic
        );
    END COMPONENT;

   --Inputs
   signal A : std_logic := '0';
   signal B : std_logic := '0';
   signal C : std_logic := '0';

    --Outputs
   signal Y : std_logic;
BEGIN
   uut: numdet PORT MAP (
          A => A,
          B => B,
          C => C,
          Y => Y
        );

   -- Stimulus process
   stim_proc: process
   begin
        A <= '0';
        B <= '0';
        C <= '0';
      wait for 100 ns;
        A <= '0';
        B <= '0';
        C <= '1';
      wait for 100 ns;
        A <= '0';
        B <= '1';
        C <= '0';
      wait for 100 ns;
        A <= '0';
        B <= '1';
        C <= '1';
      wait for 100 ns;
        A <= '1';
        B <= '0';
        C <= '0';
      wait for 100 ns;
        A <= '1';
        B <= '0';
        C <= '1';
      wait for 100 ns;
        A <= '1';
        B <= '1';
        C <= '0';
      wait for 100 ns;
        A <= '1';
        B <= '1';
        C <= '1';
      wait;
   end process;
END;