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- --Watch--
- library ieee;
- use ieee.std_logic_1164.all;
- use ieee.numeric_std.all;
- use work.all;
- entity Watch is
- port(
- speed, reset, clk : in std_logic;
- sec_1,sec_10: out std_logic_vector(6 downto 0);
- min_1,min_10: out std_logic_vector(6 downto 0);
- hrs_1,hrs_10: out std_logic_vector(6 downto 0);
- tm : out std_logic_vector(15 downto 0)
- );
- end;
- architecture structural of Watch is
- signal clk_signal_0,clk_signal_1,clk_signal_2,clk_signal_3,clk_signal_4,clk_signal_5, clk_signal_6: std_logic;
- signal reset_out: std_logic;
- signal count_signal_1,count_signal_2,count_signal_3,count_signal_4,count_signal_5,count_signal_6: std_logic_vector(3 downto 0);
- begin
- --UUT binary to seven seg display
- clock1: entity clock_gen port map
- (speed=>speed, clk=>clk, reset=>reset_out, clk_out=>clk_signal_0);
- --Reset logic for watch
- reset1: entity reset_logic port map
- (reset_in => reset, hr_bin_1 => count_signal_5, hr_bin_10 => count_signal_6, reset_out=> reset_out);
- --Multi_counter for seconds 0,1..9--
- multicounter_sec_1: entity multi_counter port map
- (mode => "00", clk=>clk_signal_0,reset=>reset_out,count=>count_signal_1, cout=>clk_signal_1 );
- --Multi_counter for seconds 0,10..50--
- multicounter_sec_10: entity multi_counter port map
- (mode => "01", clk=>clk_signal_1,reset=>reset_out,count=>count_signal_2, cout=>clk_signal_2 );
- --Multi_counter for minutes 0,1..9--
- multicounter_min_1: entity multi_counter port map
- (mode => "00", clk=>clk_signal_2,reset=>reset_out,count=>count_signal_3, cout=>clk_signal_3 );
- --Multi_counter for minutes 0,10..50--
- multicounter_min_10: entity multi_counter port map
- (mode => "01", clk=>clk_signal_3,reset=>reset_out,count=>count_signal_4, cout=>clk_signal_4 );
- --Multi_counter for hours 0,1..9--
- multicounter_hr_1: entity multi_counter port map
- (mode => "00", clk=>clk_signal_4,reset=>reset_out,count=>count_signal_5, cout=>clk_signal_5 );
- --Multi_counter for hours 0,10..50--
- multicounter_hr_10: entity multi_counter port map
- (mode => "11", clk=>clk_signal_5,reset=>reset_out,count=>count_signal_6, cout=>clk_signal_6);
- --Display for seconds 0,1..9
- seg_sec_1: entity CaseBin2Sevenseg port map
- (bin=>count_signal_1, sseg=>sec_1);
- --Display for seconds 0,10..50
- seg_sec_10: entity CaseBin2Sevenseg port map
- (bin=>count_signal_2, sseg=>sec_10);
- --Display for minutes 0,1..9
- seg_min_1: entity CaseBin2Sevenseg port map
- (bin=>count_signal_3, sseg=>min_1);
- --Display for minutes 0,10..50
- seg_min_10: entity CaseBin2Sevenseg port map
- (bin=>count_signal_4, sseg=>min_10);
- --Display for hours 0,1..9
- seg_hr_1: entity CaseBin2Sevenseg port map
- (bin=>count_signal_5, sseg=>hrs_1);
- --Display for hours 0,10..50
- seg_hr_10: entity CaseBin2Sevenseg port map
- (bin=>count_signal_6, sseg=>hrs_10);
- --tm signal out--
- tm<=count_signal_6 & count_signal_5 & count_signal_4 & count_signal_3;
- end;
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