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Apr 22nd, 2018
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VHDL 2.83 KB | None | 0 0
  1. --Watch--
  2. library ieee;
  3. use ieee.std_logic_1164.all;
  4. use ieee.numeric_std.all;
  5. use work.all;
  6.  
  7. entity Watch is
  8. port(
  9.     speed, reset, clk : in std_logic;
  10.     sec_1,sec_10: out std_logic_vector(6 downto 0);
  11.     min_1,min_10: out std_logic_vector(6 downto 0);
  12.     hrs_1,hrs_10: out std_logic_vector(6 downto 0);
  13.     tm : out std_logic_vector(15 downto 0)
  14. );
  15. end;
  16.  
  17. architecture structural of Watch is
  18. signal clk_signal_0,clk_signal_1,clk_signal_2,clk_signal_3,clk_signal_4,clk_signal_5, clk_signal_6: std_logic;
  19. signal reset_out: std_logic;
  20. signal count_signal_1,count_signal_2,count_signal_3,count_signal_4,count_signal_5,count_signal_6: std_logic_vector(3 downto 0);
  21.  
  22. begin
  23. --UUT binary to seven seg display
  24. clock1: entity clock_gen port map
  25. (speed=>speed, clk=>clk, reset=>reset_out, clk_out=>clk_signal_0);
  26.  
  27. --Reset logic for watch
  28. reset1: entity reset_logic port map
  29. (reset_in => reset, hr_bin_1 => count_signal_5, hr_bin_10 => count_signal_6, reset_out=> reset_out);
  30.  
  31. --Multi_counter for seconds 0,1..9--
  32. multicounter_sec_1: entity multi_counter port map
  33. (mode => "00", clk=>clk_signal_0,reset=>reset_out,count=>count_signal_1, cout=>clk_signal_1 );
  34.  
  35. --Multi_counter for seconds 0,10..50--
  36. multicounter_sec_10: entity multi_counter port map
  37. (mode => "01", clk=>clk_signal_1,reset=>reset_out,count=>count_signal_2, cout=>clk_signal_2 );
  38.  
  39. --Multi_counter for minutes 0,1..9--
  40. multicounter_min_1: entity multi_counter port map
  41. (mode => "00", clk=>clk_signal_2,reset=>reset_out,count=>count_signal_3, cout=>clk_signal_3 );
  42.  
  43. --Multi_counter for minutes 0,10..50--
  44. multicounter_min_10: entity multi_counter port map
  45. (mode => "01", clk=>clk_signal_3,reset=>reset_out,count=>count_signal_4, cout=>clk_signal_4 );
  46.  
  47. --Multi_counter for hours 0,1..9--
  48. multicounter_hr_1: entity multi_counter port map
  49. (mode => "00", clk=>clk_signal_4,reset=>reset_out,count=>count_signal_5, cout=>clk_signal_5 );
  50.  
  51. --Multi_counter for hours 0,10..50--
  52. multicounter_hr_10: entity multi_counter port map
  53. (mode => "11", clk=>clk_signal_5,reset=>reset_out,count=>count_signal_6, cout=>clk_signal_6);
  54.  
  55. --Display for seconds 0,1..9
  56. seg_sec_1: entity CaseBin2Sevenseg port map
  57. (bin=>count_signal_1, sseg=>sec_1);
  58.  
  59. --Display for seconds 0,10..50
  60. seg_sec_10: entity CaseBin2Sevenseg port map
  61. (bin=>count_signal_2, sseg=>sec_10);
  62.  
  63. --Display for minutes 0,1..9
  64. seg_min_1: entity CaseBin2Sevenseg port map
  65. (bin=>count_signal_3, sseg=>min_1);
  66.  
  67. --Display for minutes 0,10..50
  68. seg_min_10: entity CaseBin2Sevenseg port map
  69. (bin=>count_signal_4, sseg=>min_10);
  70.  
  71. --Display for hours 0,1..9
  72. seg_hr_1: entity CaseBin2Sevenseg port map
  73. (bin=>count_signal_5, sseg=>hrs_1);
  74.  
  75. --Display for hours 0,10..50
  76. seg_hr_10: entity CaseBin2Sevenseg port map
  77. (bin=>count_signal_6, sseg=>hrs_10);
  78.  
  79. --tm signal out--
  80. tm<=count_signal_6 & count_signal_5 & count_signal_4 & count_signal_3;
  81.  
  82. end;
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