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lasthunter657

Untitled

Oct 16th, 2021
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  1. --top entity
  2. LIBRARY ieee;
  3. USE ieee.std_logic_1164.ALL;
  4. USE ieee.numeric_std.ALL;
  5.  
  6. ENTITY multi_2_2 IS
  7.     PORT (
  8.         factor1, factor2 : IN STD_LOGIC_VECTOR(0 TO 3) := "0101";
  9.         outcome : OUT STD_LOGIC := '0'
  10.  
  11.     );
  12. END multi_2_2;
  13.  
  14. ARCHITECTURE rtl OF multi_2_2 IS
  15.  
  16.     COMPONENT xorgate
  17.         PORT (
  18.             xora, xorb : IN std_logic_vector(0 to 1);
  19.             xorC : OUT std_logic_vector(0 to 1)
  20.         );
  21.     END COMPONENT;
  22.  
  23.     COMPONENT orgate IS
  24.         PORT (
  25.             ora, orb : IN std_logic_vector(0 to 1);
  26.             orC : OUT std_logic_vector(0 to 1)
  27.         );
  28.     END COMPONENT;
  29.     SIGNAL or1output, or2output, xoroutput : std_logic_vector(0 TO 1) := (OTHERS => '0');
  30.     SIGNAL allout : std_logic_vector(0 to 7) := (OTHERS => '0');
  31.     ALIAS out1 : STD_LOGIC_VECTOR(0 TO 1) IS allout(0 TO 1);
  32.     ALIAS out2 : STD_LOGIC_VECTOR(0 TO 1) IS allout(2 TO 3);
  33.     ALIAS out3 : STD_LOGIC_VECTOR(0 TO 1) IS allout(4 TO 5);
  34.     ALIAS out4 : STD_LOGIC_VECTOR(0 TO 1) IS allout(6 TO 7);
  35.  
  36. BEGIN
  37.     allout <= STD_LOGIC_VECTOR(unsigned(factor1) * unsigned(factor2));
  38.  
  39.     firstor : orgate PORT MAP(ora => out1, orb => out2, orC => or1output);
  40.     secondor : orgate PORT MAP(ora => out3, orb => out4, orC => or2output);
  41.     firstxor : xorgate PORT MAP(xora => or1output, xorb => or2output, xorC => xoroutput);
  42.      
  43.     PROCESS (xoroutput)
  44.     BEGIN
  45.  
  46.         CASE xoroutput IS
  47.  
  48.             WHEN "00" => outcome <= '0';
  49.             WHEN "01" => outcome <= '1';
  50.             WHEN "10" => outcome <= '1';
  51.             WHEN "11" => outcome <= '0';
  52.             WHEN OTHERS => outcome <= '0';
  53.  
  54.         END CASE;
  55.    
  56.  
  57. END PROCESS;
  58. END ARCHITECTURE;
  59.  
  60.  
  61. -- orgate
  62.  
  63.  
  64. LIBRARY ieee;
  65. USE ieee.std_logic_1164.ALL;
  66. USE ieee.numeric_std.ALL;
  67.  
  68. ENTITY orgate IS
  69.     PORT (
  70.         ora, orb : IN STD_LOGIC_VECTOR(0 TO 1);
  71.         orC : OUT STD_LOGIC_VECTOR(0 TO 1)
  72.     );
  73. END orgate;
  74.  
  75. ARCHITECTURE RTL OF orgate IS
  76.  
  77. BEGIN
  78.  
  79.     orC <= ora OR orb;
  80. END ARCHITECTURE;
  81.  
  82.     -- xor gate
  83.  
  84.    
  85.  
  86. LIBRARY ieee;
  87. USE ieee.std_logic_1164.ALL;
  88. USE ieee.numeric_std.ALL;
  89.  
  90. ENTITY xorgate IS
  91.     PORT (
  92.         xora ,xorb: IN std_logic_vector(0 to 1);
  93.         xorC : OUT std_logic_vector(0 to 1)
  94.     );
  95. END xorgate;
  96.  
  97. ARCHITECTURE RTL OF xorgate IS
  98.  
  99. BEGIN
  100.  
  101.     xorC <= xora xor xorb;
  102.  
  103.  
  104. END ARCHITECTURE;
  105.  
  106.  
  107.  
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