Stage 1 (faulty ?) loader

SECTION "Init vector", ROM0[$100]

InitVect::
    di
    jr Start
    nop

    ds $150 - $104

Start::
    cp $11
    jr nz, Start ; Lock-up if not CGB

    ; Ensure we're in VBlank
.waitVBlank
    ldh a, [$FF44] ; LY
    cp $90
    jr nz, .waitVBlank

    ld hl, $8000
    ld c, $10
    xor a
.clearTile0
    ld [hli], a
    dec c
    jr nz, .clearTile0

    ld hl, $9800
    ; xor a
    ld [hl], a
    inc a ; ld a, 1
    ; Load VRAM bank 1
    ld [$FF4F], a ; VBK
    ld [hl], 0

    ld a, $80
    ld c, $68
    ld [c], a ; BGPI
    inc c
    add a, a
    ld [c], a ; BGPD
    ld [c], a ; BGPD


    ld c, $51
    ; Init HDMA src, just in case... doesn't matter, though
    xor a
    ld [c], a ; HDMA1
    inc c
    ld [c], a ; HDMA2
    inc c
    ; Init HDMA dest to end of VRAM bank 1
    ld a, $1F
    ld [c], a ; HDMA3
    inc c
    ld a, $F0
    ld [c], a ; HDMA4

    ld b, (($20 + $B0 + $110) / $10 - 1) | $80
    rst $00 ; DoHDMA


    ld a, $0A
    ld [$0000], a ; SRAMEnable
    ld d, $00
    xor a
.copySRAM
    ; Assume a == d
    ld [$4000], a ; SRAMBank

    ld a, $A0
    ld [$FF51], a ; HDMA1
    xor a
    ld [$FF52], a ; HDMA2

    ld b, $FF
    rst $00 ; HDMA one half of SRAM over itself
    rst $00 ; ...same

    inc d
    ld a, d
    cp 4
    jr nz, .copySRAM


    ; Fill a WRAM buffer with $FF for next HDMA
    ld hl, $C000
    ld bc, $330
.fillBuf
    ld a, $FF
    ld [hli], a
    dec bc
    ld a, b
    or c
    jr nz, .fillBuf

    ld a, $C0
    ld [$FF51], a ; HDMA1
    xor a
    ld [$FF52], a ; HDMA2
    ld b, ($33 - 1) | $80
    rst $00 ; HDMA over a buffer holding masks for the registers


    ld c, $68
    ld a, $80
    ld [c], a ; BGPI
    inc c
.waitPaletteWrite1
    ld a, [$FF41] ; STAT
    and 2
    jr nz, .waitPaletteWrite1
    ; Set blue component of BG to 0x1F to signal Stage 2 completion
    ld a, $1F
    ld [c], a


    ; Enter Stage 2

    ld c, $51
    ld a, HIGH(Stage2Payload)
    ld [c], a ; HDMA1
    inc c
    ld a, LOW(Stage2Payload)
    ld [c], a ; HDMA2
    inc c
    ld a, $AC
    ld [c], a ; HDMA3
    inc c
    ld a, $10
    ld [c], a ; HDMA4
    ld b, $80
    rst $00


.waitPaletteWrite2
    ld a, [$FF41] ; STAT
    and 2
    jr nz, .waitPaletteWrite2
    ; Set red component of BG to $1F to signal Stage 2 completion
    ld a, $1F << 2
    ld [$FF69], a ; BGPD


    ; Lock up, wait for user to touch bottom screen

    jr @



SECTION "Do HDMA rst", ROM0[$000]

DoHDMA::
    ld c, $41

.waitHBlank
    ld a, [c] ; STAT
    and 3
    jr nz, .waitHBlank

.waitNotHBlank
    ld a, [c] ; STAT
    and 3
    jr z, .waitNotHBlank

    ld c, $55
    ld a, b
    ld [c], a ; HDMA5

.waitHDMAEnd
    ld a, [c] ; HDMA5
    add a, a
    jr nc, .waitHDMAEnd

    ret

    ; Also eats up rst 08 and rst 10



SECTION "Stage 2 payload", ROM0

Stage2Payload::
    db $bc, $43, $94, $08, $41, $41, $41, $41


SECTION "Ensure 1MB ROM", ROMX,BANK[$3F]
    db 0