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-- Company:
-- Engineer:
--
-- Create Date:    11:27:52 06/04/2019
-- Design Name:
-- Module Name:    mux_wybierajacy_cyfre_z_blank - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity mux_wybierajacy_cyfre_z_blank is
    Port ( switch : in  STD_LOGIC;
           wejscie : in  STD_LOGIC_VECTOR (3 downto 0);
           wyjscie : out  STD_LOGIC_VECTOR (3 downto 0));
end mux_wybierajacy_cyfre_z_blank;

architecture Behavioral of mux_wybierajacy_cyfre_z_blank is
signal blank : std_logic_vector(3 downto 0):="1010";

begin
with switch select
    wyjscie <= wejscie when '0',
                  blank when others;


end Behavioral;