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- IntBase_Dly_Clk <= IntRx_SysClk;
- ---------------------------------------------------------------------------------------------
- -- Use of PHY_RDEN.
- -- Use of PHY_RDEN is TIME and MIG and thus these signals must be tied HIGH all the time
- IntBase_Tx_Phy_Rden <= LowVec(3 downto 0);
- IntBase_Rx_Phy_Rden <= HighVec(3 downto 0);
- ---------------------------------------------------------------------------------------------
- -- # Clock Reset - RIU State machine
- -- In the non-wizard design the clocking and RIU stuff happens from within the Clock_Reset
- -- hierarchical block. But in the the wizard design the Clock_Reset hierarchical block is
- -- not needed since PLL and reset sequencers are included in the cores.
- -- What is not included in the cores is the RIU accessing state machine, so that has been
- -- extracted from the Clock_Reset block and is used here in with the wizard design.
- -- The *Clock_Reset.vhd* source can be found in the /Libraries/clkrst_lib folder.
- -- The *Riu_StateMach.vhd* can also be found in that folder.
- --
- -- The clocks of the *Riu_StateMach* hierarchical block are no longer outputs but inputs.
- -- Why? Well:
- -- All PLL and reset stuff is assembled into the IO IP cores generated by the HSSIO-Wiz.
- -- Since clocks are no longer generated together with the state machine, the clocks
- -- for the state machine need to come from outside the file, from the IP cores.
- --
- -- ## Pin and attribute description
- -- - C_InSimulation : Attribute to force the RIU state machine in a simulation mode.
- -- : the state machine is partially overrules and only provides Fixed
- -- : values form the read registers.
- -- - ClockIn : RIU clock input, must be supplied by the HSSIO core
- -- - ResetIn : Reset input from external, goes also the the HSSIO cores
- -- - Tx_Dly_Rdy : TX: Input from the HSSO core (BITSLICE_CONTROL output).
- -- - Tx_Vtc_Rdy : TX: Input from the HSSO core (BITSLICE_CONTROL output).
- -- - Tx_Bsc_EnVtc : TX: Output to the HSSIO core (input for the BISTLICE_CONTROL).
- -- - Tx_Bs_EnVtc : TX: Output to the bitslices (Input for the BITSLICEs).
- -- - Rx_Dly_Rdy : RX: Input from the HSSO core (BITSLICE_CONTROL output).
- -- - Rx_Vtc_Rdy : RX: Input from the HSSO core (BITSLICE_CONTROL output).
- -- - Rx_Bsc_EnVtc : RX: Output to the HSSIO core (input for the BISTLICE_CONTROL).
- -- - Rx_Bs_EnVtc : RX: Output to the bitslices (Input for the BITSLICEs).
- -- - Tx_WrClk : input, Application clock generated by the TX HSSIO core PLL
- -- - Rx_SysClk : input, Application clock generated by the RX HSSIO core PLL
- -- - Tx_Locked : Input, signal generated by the HSSIO core.
- -- - Rx_Locked : Input, signal generated by the HSSIO core.
- -- - Tx_LogicRst : output, Reset for application logic generated by the state machine.
- -- - Rx_LogicRst : output, Reset for application logic generated by the state machine.
- -- - Riu_* : RIU access ports.
- -- : There is one RIU per nibble, thus two RIU per byte.
- -- - Riu_Prsnt : Input, normally indicates if a RIU interface is present.
- -- : Not used in the HSSIO cores. RIU presence is there set
- -- : by a tick-box in the wizard.
- -- : The signals are tied high or low in an upper level.
- --============================================================================================
- Byte_TopWizard_RxTx_I_Riu_StateMach : entity clkrst_lib.Riu_StateMach
- generic map (
- C_InSimulation => C_InSimulation
- )
- port map (
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