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-- Company:
-- Engineer:
--
-- Create Date:    11:45:48 05/21/2019
-- Design Name:
-- Module Name:    mux4na1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity mux4na1 is
    Port ( wejscie : in  STD_LOGIC_VECTOR (1 downto 0);
           s0 : in  STD_LOGIC_VECTOR (3 downto 0);
           s1 : in  STD_LOGIC_VECTOR (3 downto 0);
           s2 : in  STD_LOGIC_VECTOR (3 downto 0);
           s3 : in  STD_LOGIC_VECTOR (3 downto 0);
           wyjscie : out  STD_LOGIC_VECTOR (3 downto 0));
end mux4na1;

architecture Behavioral of mux4na1 is

begin

with wejscie select
    wyjscie <= s0 when "00",
                  s1 when "01",
                  s2 when "10",
                  s3 when others;


end Behavioral;