when propagate =>
                    debug <= "000000100";
                    SCK <= '1'; -- rising edge (or first bit)
                    SSEL <= '0'; -- active low
                    MOSI <= MOSI_PAR_reg(to_integer(count)); -- hold for two half periods

                    -- serial clock rate
                    if count_clocks = serial_clock_rate then
                        count_clocks <= (others => '0');
                        state <= capture; -- read after write
                    else
                        state <= propagate; -- apparently needed to reduce logic
                    end if;

                when capture =>
                    debug <= "000001000";
                    SCK <= '0'; -- falling edge
                    SSEL <= '0'; -- active low
                    MOSI <= MOSI_PAR_reg(to_integer(count)); -- hold for two half periods
                    MISO_PAR(to_integer(count)) <= MISO; -- read from slave

                    -- serial clock rate
                    if count_clocks = serial_clock_rate then
                        count_clocks <= (others => '0');
                        count <= count - 1; -- progress the countdown
                        if count = 0 then
                            state <= finalize; -- that was the last bit
                        else
                            state <= propagate; -- more bits
                        end if;
                    else
                        state <= capture; -- apparently needed to reduce logic
                    end if;