library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity MinMax is
    Port ( clk : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           data : in  STD_LOGIC_VECTOR (7 downto 0);
           enable : in  STD_LOGIC;
           min : out  STD_LOGIC_VECTOR (7 downto 0);
           min_line : out  STD_LOGIC_VECTOR (7 downto 0);
           max : out  STD_LOGIC_VECTOR (7 downto 0);
           max_line : out  STD_LOGIC_VECTOR (7 downto 0));
end MinMax;

architecture Behavioral of MinMax is
signal cnt,qmin,qmax : std_logic_vector(7 downto 0);
begin

        process (clk,enable)
        begin
                if rising_edge(clk) then
                        if reset = '1' then
                                cnt <= (others => '0');
                        elsif enable = '1' then
                                cnt <= cnt + 1;
                        end if;
                end if;
        end process;

-----------------------------------------------------------------------------------------------

        process (clk,reset,enable,data)
        begin
                if rising_edge(clk) then
                        if reset = '1' then
                                qmin <= (others => '1');
                        elsif enable = '1' then
                                if data <= qmin then
                                    qmin <= data;
                                end if;
                        end if;
                end if;
        end process;
        min <= qmin;
        process (clk,reset,enable,data)
        begin
                if rising_edge(clk) then
                        if reset = '1' then
                                min_line <= (others => '0');
                        elsif enable = '1' then
                                if data <= qmin then
                                    min_line <= cnt;
                                end if;
                        end if;
                end if;
        end process;

-----------------------------------------------------------------------------------------------

        process (clk,reset,enable,data)
        begin
                if rising_edge(clk) then
                        if reset = '1' then
                                qmax <= (others => '0');
                        elsif enable = '1' then
                                if data >= qmax then
                                    qmax <= data;
                                end if;
                        end if;
                end if;
        end process;
        max <= qmax;

        -- proces ma wygenerowac rejestr, ktory zatrzaskuje numer linijki z wartoscia max
        -- proces dziala synchronicznie wzgledem sygnalu zegarowego clk,
        -- wiec jest ustawiany poprzednimi wartosciami (z przed taktu zegara), ktore juz nie sa aktualne)
        -- dlatego wartosc max_line jest o 1 mniejsza niz cnt - co jest rzecza porzadana, poniewaz numeracja lini jest od 0 do n-1 (gdzie n to liczba lini).
        process (clk,reset,enable,data)
        begin
                if rising_edge(clk) then
                        if reset = '1' then
                                max_line <= (others => '0');
                        elsif enable = '1' then
                                if data >= qmax then
                                    max_line <= cnt;
                                end if;
                        end if;
                end if;
        end process;


end Behavioral;