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-- Company:
-- Engineer:
--
-- Create Date:    18:13:05 12/10/2011
-- Design Name:
-- Module Name:    instr_rom - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity instr_rom is
    Generic (
        pData_width : integer := 15;
        pAddress_width : integer := 5;
        pNO_Words : integer := 32);
    Port ( iA : in  STD_LOGIC_VECTOR (paddress_width-1 downto 0);
           oQ : out  STD_LOGIC_VECTOR (pdata_width-1 downto 0));
end instr_rom;

architecture Behavioral of instr_rom is
    type tRAM is array (0 to pno_words-1) of std_logic_vector (pdata_width-1 downto 0);
    signal sRAM: tRAM :=("000110001001000","000001000001000","001000000000000","000110001001000",
                                "000001000001000","001000000000000","001000000000000","000110001001000",
                                "000001000001000","001000000000000","001000000000000","001000000000000",
                                "000110001001000","000001000001000","001000000000000","001000000000000",
                                "001000000000000","001000000000000","110000000000000","000000000000000",
                                "000000000000000","000000000000000","000000000000000","000000000000000",
                                "000000000000000","000000000000000","000000000000000","000000000000000",
                                "000000000000000","000000000000000","000000000000000","000000000000000");
    signal sAddress : integer range 0 to pno_words-1;
    signal sData : std_logic_vector (14 downto 0);

begin
    oQ <= sram(conv_integer(iA));

end Behavioral;