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- LIBRARY ieee;
- USE ieee.std_logic_1164.all;
- USE ieee.std_logic_arith.all;
- ENTITY test_bench IS
- END ENTITY test_bench;
- ARCHITECTURE a OF test_bench IS
- signal tbclk : std_logic;
- signal tbrst : std_logic:= '1';
- signal tbdout : std_logic_vector(1 downto 0);
- signal syncro : std_logic;
- signal info : std_logic:= '1';
- component lab91 IS
- port( clk : in STD_LOGIC;
- srst : in STD_LOGIC;
- info : in STD_LOGIC;
- coded : out STD_LOGIC_VECTOR (1 downto 0));
- END component;
- BEGIN
- generate_clk : process begin
- loop
- tbclk <= '0';
- wait for 25 ns;
- tbclk <= '1';
- wait for 25 ns;
- end loop;
- end process;
- generate_rst : process begin
- tbrst <= '1', '0' after 125 ns;
- wait;
- end process;
- process(tbclk) begin
- if rising_edge(tbclk) then
- syncro <= tbrst;
- end if;
- end process;
- b : lab91
- port map ( clk => tbclk,
- srst => syncro,
- info => info,
- coded => tbdout);
- END ARCHITECTURE a;
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