library IEEE;
use IEEE.std_logic_1164.all;

entity and4_vhdl is

    port(A : in std_logic;
         B : in std_logic;
            C : in std_logic;
            D : in std_logic;
         Y : out std_logic);

end and4_vhdl;

architecture andLogic of and4_vhdl is

 begin

    Y <= (not A) AND (not B) AND (not C) AND (not D);

end andLogic;

-- Aunque se llame AND, tiene quatro entradas en logica negativa --