memory.vhdl

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity memory is

    port (
        clk : in std_logic;

        write_enable : in  std_logic;
        address      : in  std_logic_vector(15 downto 0);
        data_write   : in  std_logic_vector(7 downto 0);
        data_read    : out std_logic_vector(7 downto 0));

end entity memory;

architecture behavioral of memory is

    -- ROM address space in hex: 0000-3fff
    -- RAM address space in hex: 4000-ffff
    type rom_t is array (0 to 16#3fff#) of std_logic_vector(7 downto 0);
    type ram_t is array (16#4000# to 16#ffff#) of std_logic_vector(7 downto 0);

    -- ROM contains a machine code program. ROM is constant so it cannot
    -- be changed.
    constant rom : rom_t := (

        x"00",                          -- 0000: NOP
        x"2b", x"04", x"00",            -- 0001: JMP 0004
        x"1f",                          -- 0004: IN
        x"2b", x"08", x"00",            -- 0005: JMP 0008
          x"24",                                     --
          x"2b", x"13", x"00",             --
          x"25",                             -- 12
          x"2b", x"13", x"00",             --
          x"26",                                     -- 16
          x"2c", x"20", x"00",               --
          x"29",                                     -- 20
        x"2c", x"24", x"00",                --
          x"2b", x"27", x"00",             --
          x"28",                                     -- 27
        others => x"00");

    -- RAM is a signal, not a constant, so it can be modified.
    signal ram : ram_t;

    signal rom_data_read    : std_logic_vector(7 downto 0);
    signal ram_data_read    : std_logic_vector(7 downto 0);
    signal ram_selected     : std_logic;
    signal ram_selected_reg : std_logic;

begin  -- architecture behavioral

    -- ROM: 0000 <= address <= 3fff (decimal 0 <= address <= 16383)
    -- RAM: 4000 <= address <= ffff (decimal 16384 <= address <= 65535)
    -- The most-significant two bits of the address are thus zero for ROM,
    -- and non-zero for RAM.

    ram_selected <= '0' when address(15 downto 14) = "00" else
                    '1';
    data_read <= rom_data_read when ram_selected_reg = '0' else
                 ram_data_read;

    rom_process : process (clk) is
        variable addr : integer range 16#0000# to 16#3fff#;
    begin
        if rising_edge(clk) then
            if ram_selected = '0' then
                addr          := to_integer(unsigned(address));
                rom_data_read <= rom(addr);
            end if;
        end if;
    end process rom_process;

    ram_process : process (clk) is
        variable addr : integer range 16#4000# to 16#ffff#;
    begin
        if rising_edge(clk) then
            if ram_selected = '1' then
                addr := to_integer(unsigned(address));
                if write_enable = '1' then
                    ram(addr) <= data_write;
                end if;
                ram_data_read <= ram(addr);
            end if;
        end if;
    end process ram_process;

    ram_selected_process : process (clk) is
    begin
        if rising_edge(clk) then
            ram_selected_reg <= ram_selected;
        end if;
    end process ram_selected_process;

end architecture behavioral;