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- --
- -- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
- --
- -- This file contains confidential and proprietary information
- -- of Xilinx, Inc. and is protected under U.S. and
- -- international copyright and other intellectual property
- -- laws.
- --
- -- DISCLAIMER
- -- This disclaimer is not a license and does not grant any
- -- rights to the materials distributed herewith. Except as
- -- otherwise provided in a valid license issued to you by
- -- Xilinx, and to the maximum extent permitted by applicable
- -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
- -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
- -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
- -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
- -- (2) Xilinx shall not be liable (whether in contract or tort,
- -- including negligence, or under any other theory of
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- -- by a third party) even if such damage or loss was
- -- reasonably foreseeable or Xilinx had been advised of the
- -- possibility of the same.
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- -- CRITICAL APPLICATIONS
- -- Xilinx products are not designed or intended to be fail-
- -- safe, or for use in any application requiring fail-safe
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- -- systems, Class III medical devices, nuclear facilities,
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- -- Applications"). Customer assumes the sole risk and
- -- liability of any use of Xilinx products in Critical
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- --
- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
- -- PART OF THIS FILE AT ALL TIMES.
- --
- ------------------------------------------------------------------------------
- -- User entered comments
- ------------------------------------------------------------------------------
- -- None
- --
- ------------------------------------------------------------------------------
- -- "Output Output Phase Duty Pk-to-Pk Phase"
- -- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
- ------------------------------------------------------------------------------
- -- CLK_OUT1___100.000______0.000______50.0______200.000____150.000
- -- CLK_OUT2____80.000______0.000______50.0______450.000____150.000
- --
- ------------------------------------------------------------------------------
- -- "Input Clock Freq (MHz) Input Jitter (UI)"
- ------------------------------------------------------------------------------
- -- __primary_________100.000____________0.010
- -- The following code must appear in the VHDL architecture header:
- ------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
- component core
- port
- (-- Clock in ports
- CLK_IN1 : in std_logic;
- -- Clock out ports
- CLK_OUT1 : out std_logic;
- CLK_OUT2 : out std_logic;
- -- Status and control signals
- RESET : in std_logic;
- LOCKED : out std_logic
- );
- end component;
- -- COMP_TAG_END ------ End COMPONENT Declaration ------------
- -- The following code must appear in the VHDL architecture
- -- body. Substitute your own instance name and net names.
- ------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
- your_instance_name : core
- port map
- (-- Clock in ports
- CLK_IN1 => CLK_IN1,
- -- Clock out ports
- CLK_OUT1 => CLK_OUT1,
- CLK_OUT2 => CLK_OUT2,
- -- Status and control signals
- RESET => RESET,
- LOCKED => LOCKED);
- -- INST_TAG_END ------ End INSTANTIATION Template ------------
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