int32_t
set_sys_clk(void)
{
  RCC->CR |= RCC_CR_HSEON;
  FLASH->ACR |= FLASH_ACR_PRFTBE;
  FLASH->ACR |= FLASH_ACR_LATENCY;

  RCC->CFGR |= RCC_CFGR_PLLSRC_HSE_PREDIV;
  RCC->CFGR |= RCC_CFGR_PLLMUL6;
  while(!(RCC->CR & RCC_CR_HSERDY));

  RCC->CR |= RCC_CR_PLLON;
  while (!(RCC->CR & RCC_CR_PLLRDY));
  RCC->CFGR |= RCC_CFGR_SW_PLL;
  while (!(RCC->CFGR & RCC_CFGR_SWS_PLL ));

  RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN
          | RCC_AHBENR_GPIOCEN  | RCC_AHBENR_GPIODEN
          | RCC_AHBENR_GPIOEEN;

  return 0;
}