Advertisement
Not a member of Pastebin yet?
Sign Up,
it unlocks many cool features!
- library ieee;
- use ieee.std_logic_1164.all;
- use ieee.numeric_std.all;
- entity example is
- port (Reset : in std_logic;
- SysClk : in std_logic;
- zbroji : in std_logic;
- oduzmi : in std_logic;
- ulaz_broj : in std_logic;
- oduzima : out std_logic;
- ucitanPrvi : out std_logic;
- broj1 : out std_logic
- );
- end example;
- architecture Behavioral of example is
- -- Delayed version of input signals (1 clock cycle delay)
- signal zbroji_d : std_logic;
- signal oduzmi_d : std_logic;
- signal zbrojiRE : std_logic;
- signal oduzmiRE : std_logic;
- begin
- -- Generate 1 clock cycle delayed version of
- -- signals we want to detect the rising edge
- -- Assumes active high reset
- -- Note: You should only use the rising_edge macro
- -- on an actual global or regional clock signal. FPGA's and
- -- ASICs place timing constraints on defined clock signals
- -- that make it possible to use rising_edge, otherwise, we have
- -- to generate our own rising edge signals by comparing delayed
- -- versions of a signal with the current signal.
- -- Also, with any respectable synthesizer / simulator using
- -- rising_edge is almos exactly the same as (clk'event and clk='1')
- -- except rising_edge only returns a '1' when the clock makes a
- -- valid '0' to '1' transition. (see link below)
- EdgeDetectProc : process (Reset, SysClk)
- begin
- if Reset = '1' then
- zbroji_d <= '0';
- oduzmi_d <= '0';
- elsif rising_edge(SysClk) then
- zbroji_d <= zbroji;
- oduzmi_d <= oduzmi;
- end if;
- end process EdgeDetectProc;
- -- Assert risinge edge signals for one clock cycle
- zbrojiRE <= '1' when zbroji = '1' and zbroji_d = '0' else '0';
- oduzmiRE <= '1' when oduzmi = '1' and oduzmi_d = '0' else '0';
- -- Assumes that you want a single cycle pulse on ucitanPrvi on the
- -- rising edege of zbroji or oduzmi;
- ucitanPrvi <= zbrojiRE or oduzmiRE;
- -- Based on your example, I can't tell what you want to do with the
- -- broj1 signal, but this logic will drive broj1 with ulaz_broj on
- -- either the zbroji or oduzmi rising edge, otherwise '0'.
- broj1 <= ulaz_broj when zbrojiRE = '1' else
- ulaz_broj when oduzmiRE = '1' else
- '0';
- -- Finally, it looks like you want to clear oduzima on the rising
- -- edge of zbroji and assert oduzima on the rising edge of
- -- oduzmi
- LatchProc : process (Reset, SysClk)
- begin
- if Reset = '1' then
- oduzima <= '0';
- elsif rising_edge(SysClk) then
- if zbrojiRE = '1' then
- oduzima <= '0';
- elsif oduzmiRE = '1' then
- oduzima <= '1';
- end if;
- end if;
- end process LatchProc;
- end Behavioral;
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement