[VHDL] D Flip-flop w/ CE and Async CLEAR/PRESET

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-- Company:          F T N
-- Engineer:         Milan Nedic
--
-- Create Date:    01:14:55 04/02/2017
-- Design Name:
-- Module Name:    D_FLIPFLOP_CE_ASYNC_CLEAR_PRESET_BEH - Behavioral

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity D_FLIPFLOP_CE_ASYNC_CLEAR_PRESET_BEH is
    Port ( clk :                in  STD_LOGIC;
           d :                  in  STD_LOGIC;
           ce :                 in  STD_LOGIC;
           clear :              in  STD_LOGIC;
           preset :             in  STD_LOGIC;
           q :                  out  STD_LOGIC
            );
end D_FLIPFLOP_CE_ASYNC_CLEAR_PRESET_BEH;

architecture Behavioral of D_FLIPFLOP_CE_ASYNC_CLEAR_PRESET_BEH is
begin
    -- Asynchronous PRESET and CLEAR with CLOCK ENABLE
    -- Asynchronous inputs are placed in SENSITIVITY LIST
    d_ff: process(clk, clear, preset) is
    begin
        -- First, lets check Asynchronous INPUTS
        if(clear = '1') then                                -- CLEAR has PRIORITY higher than PRESET
            q <= '0';                                       -- Sets OUTPUT to 0
        elsif(preset = '1') then                            -- PRESET has second order PRIORITY
            q <= '1';                                       -- Sets OUTPUT to 1
        else
            -- Check synchronous part...
            if(clk'event and clk = '1')then                 -- on CLOCK rising edge
                if(ce = '1') then                           -- If CLOCK ENABLE is ACTIVE
                    q <= d;                                 -- Assign INPUT value to the OUTPUT
                end if;
            end if;
        end if;
    end process;

end Behavioral;