Flip-Flop tipo D

-- Quartus II VHDL Template

library ieee;
use ieee.std_logic_1164.all;

entity ff_d is

    port
    (
        d, ck, set, rst    : in std_logic;
        q, nq  : out std_logic
    );
end ff_d;

architecture comportamental of ff_d is
begin
    process (ck, set, rst)
    begin
        if (rst='0') then q <='0'; nq <='1';
        elsif (set='0') then q<='1'; nq <='0';
        elsif (ck'event and ck='1') then q <=d; nq <= not(d);
        end if;
    end process;
end comportamental;