/********************************************* ADC Controller Details ****************************************
    1) Board ADC
    Board:              DE1-SoC (rev. F+)
    ADC Chip:           LTC2308
    ADC Clock Freq:     0.01 - 20 MHz
    Voltage Range:      0 - 5 V
    Channels:           8
    Resolution:         12 bit

    2) Available Registers
     ---------------------------------------------------------------------------------------------------------
    |   Offset in bytes    |    Register name      |    Read/Write     |    Purpose                           |
     ---------------------------------------------------------------------------------------------------------
    |           0          |         CH_0          |        R          |    Converted value of channel 0      |
    |                      |        Update         |        W          |    Update the converted values       |
     ---------------------------------------------------------------------------------------------------------
    |           4          |         CH_1          |        R          |    Converted value of channel 1      |
    |                      |      Auto-Update      |        W          |    Enables or disables auto-updating |
     ---------------------------------------------------------------------------------------------------------
    |           8          |         CH_2          |        R          |    Converted value of channel 2      |
     ---------------------------------------------------------------------------------------------------------
    |           12         |         CH_3          |        R          |    Converted value of channel 3      |
     ---------------------------------------------------------------------------------------------------------
    |           16         |         CH_4          |        R          |    Converted value of channel 4      |
     ---------------------------------------------------------------------------------------------------------
    |           20         |         CH_5          |        R          |    Converted value of channel 5      |
     ---------------------------------------------------------------------------------------------------------
    |           24         |         CH_6          |        R          |    Converted value of channel 6      |
     ---------------------------------------------------------------------------------------------------------
    |           28         |         CH_7          |        R          |    Converted value of channel 7      |
     ---------------------------------------------------------------------------------------------------------
                                                    Table 1
    3) Software Programming Model (Theory) source: Intel University Program

        3.1) Register Map

            The ADC Controller for DE-series Boards IP Core provides eight registers for reading and two for writing, as
            shown in Table 1. The eight readable registers contain the outputs from the ADC for the eight analog inputs. The
            two writable registers are used to control the ADC. Writing to the Update register triggers an update of the stored
            conversions, and writing to Auto-Update enables or disables the automatic update feature.

            3.1.1) Channel Registers
                These eight registers hold the 12-bit outputs from the eight ADC channels. They are refreshed upon completion of an
                update operation. An update operation can be triggered manually by writing to the Update register, or automatically
                by enabling the Auto-Update mode via the Auto-Update register. In Auto-Update mode, the 16th bit of the channel
                register acts as a refresh flag. After all channels are refreshed, the flags are high. Upon reading a channel, that
                channel’s flag is set to low.

            3.1.2) Update Register
                Writing any value to the Update register begins a conversion cycle on the ADC. During this time, all desired channels
                (as specified in the Platform Designer configuration wizard) are sampled. The new values become available in the
                Channel registers once the entire update operation has finished. If reads to the channel registers are attempted
                during the conversion cycle, the wait_request signal will be raised, causing the processor to stall until the update has
                finished.

            3.1.3) Auto-Update Register
                    On system startup, this register will be loaded with a zero value. Writing a ‘1’ to this register will enable autoupdating,
                while writing a ‘0’ will disable it.
                    When auto-update is enabled, the system will automatically begin another update operation after the previous one
                finishes. Additionally, if reads to the channel registers are attempted during an update operation, the stored values
                from the previous update operation will be read without waiting for the latest update to finish. This is in contrast to
                a read during an update operation triggered by the Update register, where the wait_request signal would be asserted
                until the current update operation finishes.


****************************************** end of ADC Controller Details ************************************/



#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <unistd.h>
#include <fcntl.h>
#include <sys/types.h>
#include <sys/ipc.h>
#include <sys/shm.h>
#include <sys/mman.h>
#include <sys/time.h>

#define ADC_BASE    0x000000000 // intended for pointer use


// "/dev/mem" file id
int fd;

// the adc base base
void *adc_virtual_base;

// pointer to the ADC base
volatile unsigned int * adc_base_ptr = NULL ;

int main(void) {
    // declare volatile pointers to I/O registers (volatile means that IO load and store instructions will be used
    // to access these pointer locations,
    // instead of regular memory loads and stores)

    // === get FPGA addresses ==================
    // Open /dev/mem. Please visit http://man7.org/linux/man-pages/man2/open.2.html for more details about mmap()
    if( ( fd = open( "/dev/mem", ( O_RDWR | O_SYNC ) ) ) == -1 )    {
        printf( "ERROR: could not open \"/dev/mem\"...\n" );
        return( 1 );
    }

    // get virtual addr that maps to physical. Please visit http://man7.org/linux/man-pages/man2/mmap.2.html for more details about mmap()
    adc_virtual_base = mmap( NULL, 4096, ( PROT_READ | PROT_WRITE ), MAP_SHARED, fd, ADC_BASE );
    if( adc_virtual_base == MAP_FAILED ) {
        printf( "ERROR: mmap() failed...\n" );
        close( fd );
        return(1);
    }

    adc_base_ptr = (unsigned int *) adc_virtual_base;

    // declare & intialize utility variables before using them
    int channel_values [8];     // will store channel values in each cycle

    // poll ADC
    while(1) {

        // initiate an update request by writing to the UPDATE register
        *(adc_base_ptr) = 0;

        // read values from all 8 channels
        for(int i = 0; i < 8; i++) {
            channel_values[i] = *(adc_base_ptr + i);
        }

        // print values. Only bit 11 to bit 0 are printed. Rest are ignored.
        for(int i = 0; i < 8; i++) {
            printf("Channel %2d: %04d\n", i, channel_values[i] & 0xFFF);
        }

        // new lines
        printf("\n\n");
        // clear screen before printing again
        system("clear");
        usleep(100);
    }

    // clean up our memory mapping and exit

    if( munmap( adc_virtual_base, 4096 ) != 0 ) {
        printf( "ERROR: munmap() failed...\n" );
        close( fd );
        return( 1 );
    }

    close( fd );

}