clock_gen

--------- clock_gen ---------
Library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity clock_gen is
port(
    clk         : in std_logic;
    speed       : in std_logic;
    reset       : in std_logic;
    clk_out     : out std_logic);
end clock_gen;

architecture structural of clock_gen is

begin

    CGpro: process(clk)                 -- counter process med counter som integer
        variable counter : integer := 0;
    begin
        if rising_edge(clk)then
            counter := counter + 1;     -- counter integer øges afhængigt af clockspeed
            if ((counter >= 50000000 and speed = '1') or (counter >= 250000 and speed = '0')) then
                clk_out <= '1';         -- reset ved hvert sekund eller hurtigere ved tryk på "speed"
                counter := 0;
            else
                clk_out <= '0';
            end if;
        else
        NULL;
        end if;

        if reset = '0' then             -- reset ved tryk på reset knap
            counter := 0;
            clk_out <= '0';
        else
        NULL;
        end if;

    end process;


end structural;