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Jun 28th, 2018
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VHDL 0.32 KB | None | 0 0
  1. process (CLK, RES_IN, MODE_UP)
  2.             begin
  3.                 if RES_IN = '1' then cntval <= "000000000000000000000000000";
  4.                 end if;
  5.             if (CLK'event and clk='1' and MODE_UP = '1') then
  6.                         cntval <= cntval+1;
  7.                     elsif (CLK'event and clk='1' and MODE_UP = '0') then
  8.                         cntval <= cntval-1;
  9.                     else
  10.                 end if;
  11.         end process;
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