VHDL TEST

    x6p : process

begin

x6 <= '0';

wait for 10 ns ;

x6 <= '1';

wait for 10 ns ;

end process ;

x5p : process

begin

x5 <= '0';

wait for 20 ns ;
x5 <= '1';

wait for 20 ns ;

end process ;

x4p : process

begin

x4 <= '0';

wait for 40 ns ;

x4 <= '1';

wait for 40 ns ;

end process ;

x3p : process

begin

x3 <= '0';

wait for 80 ns ;

x3 <= '1';

wait for 80 ns ;

end process ;

x2p : process

begin

x2 <= '0';

wait for 160 ns ;

x2 <= '1';

wait for 160 ns ;

end process ;

x1p : process

begin

x1 <= '0';

wait for 320 ns ;

x1 <= '1';

wait for 320 ns ;

assert false report " Pabaiga " severity failure ;

end process ;