API tools faq
paste
eh49er

Untitled

eh49er
Feb 24th, 2012
800
0
Never
Add comment
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
C 12.55 KB | None | 0 0
raw download clone embed print report
  1. void srio_init(uint laneIndex) {
  2.     int i;
  3.     uint8 temp8, temp8_2;
  4.     uint32 rxCfg, txCfg, temp;
  5.     SRIO_PE_FEATURES    peFeatures;
  6.     SRIO_OP_CAR         opCar;
  7.     lsuNum = 0;
  8.     SRIO_PLM_POLARITY_CONTROL polCtrl;
  9.  
  10. //    Qmss_QueueHnd       queueHnd;
  11. //    uint8_t             isAllocated;
  12. //    uint32_t            gargbageQueue[] = { GARBAGE_LEN_QUEUE,  GARBAGE_TOUT_QUEUE,
  13. //                                            GARBAGE_RETRY_QUEUE, GARBAGE_TRANS_ERR_QUEUE,
  14. //                                            GARBAGE_PROG_QUEUE, GARBAGE_SSIZE_QUEUE };
  15.  
  16.     /* Get the CSL SRIO Handle. */
  17.     sjlHSrio = CSL_SRIO_Open(0);
  18.  
  19.     /* Disable the SRIO Global block */
  20.     CSL_SRIO_GlobalDisable(sjlHSrio);
  21.     /* Disable each of the individual SRIO blocks. */
  22.     for(i = 0; i <= 9; i++) {
  23.         CSL_SRIO_DisableBlock(sjlHSrio, i);
  24.     }
  25.     /* Set boot complete to be 0; we are not done with the initialization. */
  26.     temp = SRIO_REGS->RIO_PER_SET_CNTL;
  27.     CSL_SRIO_SetBootComplete(sjlHSrio, 0);
  28.     temp = SRIO_REGS->RIO_PER_SET_CNTL;
  29.     /* Now enable the SRIO block and all the individual blocks also. */
  30.     CSL_SRIO_GlobalEnable(sjlHSrio);
  31.     for(i = 0; i <= 9; i++) {
  32.         CSL_SRIO_EnableBlock(sjlHSrio, i);
  33.     }
  34.  
  35.     /* Register settings after coming up in SRIO Boot Mode:
  36.      *
  37.      * PER_SER_CNTL     0x0D053860
  38.      * PER_SET_CNTL1    0x00000000
  39.      *
  40.      * GBL_EN           0x00000001
  41.      * GBL_EN_STAT      0x000007FF
  42.      *
  43.      * LSU_SETUP_REG0   0x44444444
  44.      * LSU_SETUP_REG1   0x00000000
  45.      *
  46.      */
  47.  
  48.     /* Configure SRIO ports to operate in normal mode. */
  49.     CSL_SRIO_SetNormalMode(sjlHSrio, 0);
  50.  
  51.     CSL_SRIO_SetMAUSwappingMode(sjlHSrio, 0);
  52.     CSL_SRIO_SetLSUSwappingMode(sjlHSrio, 0);
  53.  
  54.     /* Set to respond to andy target id */
  55.     CSL_SRIO_EnablePromiscuous(sjlHSrio);
  56.  
  57.     CSL_SRIO_SetAMUSwappingMode(sjlHSrio, 0);
  58.     CSL_SRIO_SetTXURXUSwappingMode(sjlHSrio, 0);
  59.  
  60.     /* Enable Automatic Priority Promotion of response packets. */
  61.     CSL_SRIO_EnableAutomaticPriorityPromotion(sjlHSrio);
  62.  
  63.     /* Set the SRIO Prescalar select to operate in the range of 313.2 to 626.4 */
  64.     CSL_SRIO_SetPrescalarSelect(sjlHSrio, 6);
  65.  
  66.     /* Unlock the Boot Configuration Kicker */
  67.     CSL_BootCfgUnlockKicker();
  68.     /* Assuming the link rate is 5000; program the PLL accordingly. [From sprugw1a (SRIO Rev A) Section 2.3.1.1 pg.41-43] */
  69.     temp =  (0 << 13) |     // CLKBYP - Clock Bypass disabled
  70.             (0 << 11) |     // LOOP_BANDWIDTH - 0 -> Freq dependent bandwidth
  71.             (0 << 10) |     // SLEEPPLL - disabled
  72.             (1 << 9) |      // VRANGE - HI/LOW VCO range
  73.             (0x28 << 1) |   // MPY - 0x28 -> 10x (for 3.125Gbps) //0x40 -> 16x (for 5Gbps) (used for 156.25 MHz ref clock)
  74.             (1 << 0);       // ENPLL - Enable PLL
  75.     CSL_BootCfgSetSRIOSERDESConfigPLL(temp);
  76.  
  77.  
  78.     /* Configure the SRIO SERDES Receive Configuration values. [From sprugw1a (SRIO Rev A) Section 2.3.1.2 pg.44-47]
  79.      * Note: SRIO Boot Mode comes up as 0x00440495 */
  80.     rxCfg = (0 << 25) |     // TESTPATTERN - disabled
  81. #ifdef LOOPBACK_TEST_MODE
  82.             (3 << 23) |     // LOOPBACK - enabled
  83. #else
  84.             (0 << 23) |     // LOOPBACK - disabled
  85. #endif
  86.             (1 << 22) |     // ENOC - enable? (initial disable)
  87.             (0 << 21) |     // EQHLD - disabled
  88.             (1 << 18) |     // EQ - 1 for Adaptive
  89.             (1 << 15) |     // CDR (Clock/Data Recovery) - 1 for Second order
  90.             (0 << 12) |     // LOS (Loss of Signal) - 0 to disable
  91.             (1 << 10) |     // ALIGN - 1 for Comma alignment enabled
  92.             (1 << 7) |      // TERM - Must be set to 1
  93.             (0 << 6) |      // INVPAIR - 0 for Normal polarity
  94.             (1 << 4) |      // RATE - 0=Full, 1=Half, 2=Quarter
  95.             (2 << 1) |      // BUSWIDTH - Always write 010b to this field to indicate a 20-bit wide parallel bus to the clock (see note on pg 46) ***6474 set to 0
  96.             (1 << 0);       // ENRX - 1 to Enable this receiver
  97.  
  98.     /* Configure the SRIO SERDES Transmit Configuration values. [From sprugw1a (SRIO Rev A) Section 2.3.1.3 pg.47-49]
  99.      * Note: SRIO Boot Mode comes up as 0x00180795 */
  100.     txCfg = (0 << 23) |     // TESTPATTERN - disabled
  101. #ifdef LOOPBACK_TEST_MODE
  102.             (3 << 23) |     // LOOPBACK - enabled
  103. #else
  104.             (0 << 23) |     // LOOPBACK - disabled
  105. #endif
  106.             (0 << 20) |     // MSYNC - Synchronization master Enables the channel as the master lane
  107.             (1 << 19) |     // FIRUPT - Transmitter pre and post cursor FIR filter update
  108.             (0 << 14) |     // TWPST1 - Adjacent post cursor Tap weight, 0-15 -> -37.5 to +37.5% in 2.5% steps
  109.             (0 << 11) |     // TWPRE - Precursor Tap weight, 0-7 -> 0 to -17.5% in 2.5% steps
  110.             (0xF << 7) |    // SWING - Output swing, 0-F See Table 2-13 (pg 48) ***Comes up as 0xF in SRIO Boot mode, 6474 set to 4
  111.             (0 << 6) |      // INVPAIR - 0 for Normal polarity
  112.             (1 << 4) |      // RATE - 0=Full, 1=Half, 2=Quarter
  113.             (2 << 1) |      // BUSWIDTH - Always write 010b to this field to indicate a 20-bit wide parallel bus to the clock (see note on pg 48) ***6474 set to 0
  114.             (1 << 0);       // ENRX - 1 to Enable this transmitter
  115.  
  116.     for(i = 0; i < 4; i++) {
  117.         /* Set the SRIO SERDES Receive Configuration. */
  118.         CSL_BootCfgSetSRIOSERDESRxConfig(i, rxCfg);
  119.  
  120.         /* Set the SRIO SERDES Transmit Configuration. */
  121.         if(laneIndex == LANE_WIDTH_1x) {
  122.             CSL_BootCfgSetSRIOSERDESTxConfig(i, txCfg | (1 << 20));
  123.         } else if(laneIndex == LANE_WIDTH_2x) {
  124.             if((i & 1) == 0) {
  125.                 /* Make Lane 0 and 2 Master Lanes (in 2x mode) */
  126.                 CSL_BootCfgSetSRIOSERDESTxConfig(i, txCfg | (1 << 20));
  127.             } else {
  128.                 CSL_BootCfgSetSRIOSERDESTxConfig(i, txCfg);
  129.             }
  130.         } else if(laneIndex == LANE_WIDTH_4x) {
  131.             if(i == 0) {
  132.                 /* Make Lane 0 Master Lane (in 4x mode) */
  133.                 CSL_BootCfgSetSRIOSERDESTxConfig(i, txCfg | (1 << 20));
  134.             } else {
  135.                 CSL_BootCfgSetSRIOSERDESTxConfig(i, txCfg);
  136.             }
  137.         }
  138.     }
  139.  
  140.     //delayCycles(5000);
  141.     while(1) {
  142.         uint32_t    status;
  143.         /* Get the SRIO SERDES Status */
  144.         CSL_BootCfgGetSRIOSERDESStatus(&status);
  145.         if (status & 0x1)
  146.             break;
  147.     }
  148.  
  149. #ifdef CHANGE_BOOT_FIELDS
  150.     /* Set the Host Device Identifier. */
  151.     CSL_SRIO_SetHostDeviceID(sjlHSrio, 0x00000001);
  152. #endif
  153.     /* Configure the component tag CSR */
  154.     CSL_SRIO_SetCompTagCSR (sjlHSrio, 0x1492);
  155.  
  156.     polCtrl.rx0Pol = 0;
  157.     polCtrl.rx1Pol = 0;
  158.     polCtrl.rx2Pol = 0;
  159.     polCtrl.rx3Pol = 0;
  160.     polCtrl.tx0Pol = 0;
  161.     polCtrl.tx1Pol = 0;
  162.     polCtrl.tx2Pol = 0;
  163.     polCtrl.tx3Pol = 0;
  164.  
  165.     for(i = 0; i < 4; i++) {
  166.         /* Set the PLM Port Silence Timer. */
  167.         CSL_SRIO_SetPLMPortSilenceTimer(sjlHSrio, i, 0x2);
  168.  
  169.         if(laneIndex == LANE_WIDTH_1x) {
  170.             /* Setup port width to be 1x mode */
  171.             CSL_SRIO_SetPLMPortPathControlMode(sjlHSrio, i, 0);
  172.             CSL_SRIO_ClearPLMPortLinkInitialized(sjlHSrio, i);
  173.             CSL_SRIO_SetPLMPortPolarityControl(sjlHSrio, i, &polCtrl);
  174.         } else if(laneIndex == LANE_WIDTH_2x) {
  175.             /* Setup port width to be 2x mode */
  176.             CSL_SRIO_SetPLMPortPathControlMode(sjlHSrio, i, 3);
  177.             if((i & 1) == 0) {
  178.                 CSL_SRIO_ClearPLMPortLinkInitialized(sjlHSrio, i);
  179.                 CSL_SRIO_SetPLMPortPolarityControl(sjlHSrio, i, &polCtrl);
  180.             }
  181.         } else if(laneIndex == LANE_WIDTH_4x) {
  182.             /* Setup port width to be 4x mode */
  183.             CSL_SRIO_SetPLMPortPathControlMode(sjlHSrio, i, 4);
  184.             if(i == 0) {
  185.                 CSL_SRIO_ClearPLMPortLinkInitialized(sjlHSrio, i);
  186.                 CSL_SRIO_SetPLMPortPolarityControl(sjlHSrio, i, &polCtrl);
  187.             }
  188.         }
  189. //        CSL_SRIO_Enable3_125GBaud(sjlHSrio, i);       //SPn_CTL2
  190.  
  191.         /* Enable Ports */
  192.         CSL_SRIO_EnableInputPort(sjlHSrio, i);
  193.         CSL_SRIO_EnableOutputPort(sjlHSrio, i);
  194.         CSL_SRIO_EnablePort(sjlHSrio, i);
  195.  
  196.         CSL_SRIO_DisablePortLockout(sjlHSrio, i);
  197.         CSL_SRIO_EnablePortErrorChecking(sjlHSrio, i);
  198.  
  199.         /* Set the PLM Port Discovery Timer. */
  200.         CSL_SRIO_SetPLMPortDiscoveryTimer(sjlHSrio, i, 0x2);
  201.         /* Reset the Port Write Reception capture. */
  202.         CSL_SRIO_SetPortWriteReceptionCapture(sjlHSrio, i, 0x0);
  203.     }
  204.  
  205.     /* Clear the LSU pending interrupts. */
  206.     CSL_SRIO_ClearLSUPendingInterrupt (sjlHSrio, 0xFFFFFFFF, 0xFFFFFFFF);
  207.     /* Set the Device Information */
  208.     CSL_SRIO_SetDeviceInfo (sjlHSrio, DEVICE_ID1_16BIT, DEVICE_VENDOR_ID, DEVICE_REVISION);
  209.     /* Set the Assembly Information */
  210.     CSL_SRIO_SetAssemblyInfo(sjlHSrio, DEVICE_ASSEMBLY_ID, DEVICE_ASSEMBLY_VENDOR_ID,
  211.                              DEVICE_ASSEMBLY_REVISION, DEVICE_ASSEMBLY_INFO);
  212.  
  213.     /* Configure the processing element features
  214.      *  The SRIO RL file is missing the Re-transmit Suppression Support (Bit6) field definition */
  215.     peFeatures.isBridge                          = 0;
  216.     peFeatures.isEndpoint                        = 0;
  217.     peFeatures.isProcessor                       = 1;
  218.     peFeatures.isSwitch                          = 0;
  219.     peFeatures.isMultiport                       = 0;
  220.     peFeatures.isFlowArbiterationSupported       = 0;
  221.     peFeatures.isMulticastSupported              = 0;
  222.     peFeatures.isExtendedRouteConfigSupported    = 1;
  223.     peFeatures.isStandardRouteConfigSupported    = 1;
  224.     peFeatures.isFlowControlSupported            = 1;
  225.     peFeatures.isCRFSupported                    = 0;
  226.     peFeatures.isCTLSSupported                   = 1;
  227.     peFeatures.isExtendedFeaturePtrValid         = 1;
  228.     peFeatures.numAddressBitSupported            = 1;
  229.     CSL_SRIO_SetProcessingElementFeatures(sjlHSrio, &peFeatures);
  230.  
  231.     /* Configure the source operation CAR */
  232.     memset ((void *) &opCar, 0, sizeof (opCar));
  233.     opCar.portWriteOperationSupport = 1;
  234.     opCar.atomicClearSupport        = 1;
  235.     opCar.atomicSetSupport          = 1;
  236.     opCar.atomicDecSupport          = 1;
  237.     opCar.atomicIncSupport          = 1;
  238.     opCar.atomicTestSwapSupport     = 1;
  239.     opCar.doorbellSupport           = 1;
  240.     opCar.dataMessageSupport        = 1;
  241.     opCar.writeResponseSupport      = 1;
  242.     opCar.streamWriteSupport        = 1;
  243.     opCar.writeSupport              = 1;
  244.     opCar.readSupport               = 1;
  245.     opCar.dataStreamingSupport      = 1;
  246.     CSL_SRIO_SetSourceOperationCAR (sjlHSrio, &opCar);
  247.  
  248.     /* Configure the destination operation CAR */
  249.     memset ((void *) &opCar, 0, sizeof (opCar));
  250.     opCar.portWriteOperationSupport  = 1;
  251.     opCar.doorbellSupport            = 1;
  252.     opCar.dataMessageSupport         = 1;
  253.     opCar.writeResponseSupport       = 1;
  254.     opCar.streamWriteSupport         = 1;
  255.     opCar.writeSupport               = 1;
  256.     opCar.readSupport                = 1;
  257.     CSL_SRIO_SetDestOperationCAR (sjlHSrio, &opCar);
  258.  
  259.     /* Set the 16 bit and 8 bit identifier for the SRIO Device. */
  260.     CSL_SRIO_SetDeviceIDCSR (sjlHSrio, DEVICE_ID1_8BIT, DEVICE_ID1_16BIT);
  261.  
  262.     /* Enable TLM Base Routing Information for Maintainance Requests & ensure that
  263.      * the BRR's can be used by all the ports. */
  264.     CSL_SRIO_SetTLMPortBaseRoutingInfo(sjlHSrio, 0, 1, 1, 1, 0);
  265.     CSL_SRIO_SetTLMPortBaseRoutingInfo(sjlHSrio, 0, 2, 1, 1, 0);
  266.     CSL_SRIO_SetTLMPortBaseRoutingInfo(sjlHSrio, 0, 3, 1, 1, 0);
  267.     CSL_SRIO_SetTLMPortBaseRoutingInfo(sjlHSrio, 1, 0, 1, 1, 0);
  268.  
  269.     /* Configure the Base Routing Register to ensure that all packets matching the
  270.      * Device Identifier & the Secondary Device Id are admitted. */
  271.     CSL_SRIO_SetTLMPortBaseRoutingPatternMatch(sjlHSrio, 0, 1, DEVICE_ID2_16BIT, 0xFFFF);
  272.     CSL_SRIO_SetTLMPortBaseRoutingPatternMatch(sjlHSrio, 0, 2, DEVICE_ID3_16BIT, 0xFFFF);
  273.     CSL_SRIO_SetTLMPortBaseRoutingPatternMatch(sjlHSrio, 0, 3, DEVICE_ID4_16BIT, 0xFFFF);
  274.     CSL_SRIO_SetTLMPortBaseRoutingPatternMatch(sjlHSrio, 1, 0, DEVICE_ID2_8BIT,  0xFF);
  275.  
  276.     /* Set the Port link timeout CSR */
  277.     CSL_SRIO_SetPortLinkTimeoutCSR(sjlHSrio, 0x000FFF);
  278.     /* Set the Port General CSR: executing as Host, Master Enabled, Discoved */
  279.     CSL_SRIO_SetPortGeneralCSR(sjlHSrio, 1, 1, 1);
  280.     /* Clear the sticky register bits. */
  281.     CSL_SRIO_SetLLMResetControl(sjlHSrio, 1);
  282.     /* Set the device id to be 0 for the Maintenance Port-Write operation
  283.      * to report errors to a system host. */
  284.     CSL_SRIO_SetPortWriteDeviceId(sjlHSrio, 0x0, 0x0, 0x0);
  285.     /* Set the Data Streaming MTU */
  286.     CSL_SRIO_SetDataStreamingMTU(sjlHSrio, 0x40);
  287.     /* Configure the path mode for the ports. */
  288.  
  289.     /* Set the LLM Port IP Prescalar. */
  290.     CSL_SRIO_SetLLMPortIPPrescalar(sjlHSrio, 0x1E);
  291.  
  292.  
  293. #ifdef LOOPBACK_TEST_MODE
  294.     SRIO_REGS->RIO_PER_SET_CNTL1 = (0xF << 4);      /* Set all ports to loopback */
  295. #else
  296.     SRIO_REGS->RIO_PER_SET_CNTL1 = 0x0;
  297. #endif
  298.  
  299.     /* Enable the peripheral. */
  300.     CSL_SRIO_EnablePeripheral(sjlHSrio);
  301.     /* Set boot complete to be 1; we are done with the initialization. */
  302.     CSL_SRIO_SetBootComplete(sjlHSrio, 1);
  303.  
  304.     debug_srio();
  305.     init_port_link(0);
  306.  
  307.     /* Initialize Constants */
  308.     ti_srio_init_const();
  309. }
Advertisement
Add Comment
Please, Sign In to add comment
Public Pastes
We use cookies for various purposes including analytics. By continuing to use Pastebin, you agree to our use of cookies as described in the Cookies Policy.  OK, I Understand
Not a member of Pastebin yet?
Sign Up, it unlocks many cool features!