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  1. library IEEE;
  2. use IEEE.STD_LOGIC_1164.ALL;
  3. entity Lab5 is
  4. Port (CLK, X1, X2: in STD_LOGIC;
  5.       C1, C2, C3: out STD_LOGIC);
  6. end Lab5;
  7.  
  8. architecture Behavioral of Lab5 is
  9. type FSM_State is(S0, S1, S2, S3, S4, S5, S6);
  10. signal State, NextState: FSM_State;
  11. begin
  12. --ниже  ПАМЯТЬ АВТОМАТА ---------------------------------------
  13. process(CLK)
  14.    begin
  15.      if rising_edge(CLK) then
  16.      if X1 = '1' then
  17.         State <= S0;
  18.      else
  19.         State <= NextState;
  20. end if;
  21. end if;
  22. end process;
  23.  
  24. --ниже  комбинационная часть АВТОМАТА-вычисление его будущего состояния  
  25. process(State, X1, X2)
  26.  begin
  27.    case State is
  28.          when S0 => if X1 = '0' and X2 = '1' then
  29.                             NextState <= S1;
  30.                       else  NextState <= S0;
  31.                       end if;
  32.          when S1 => if X1 = '0' and X2 = '0' then
  33.                             NextState <= S2;
  34.                       else  NextState <= S1;
  35.                       end if;
  36.          when S2 => if X1 = '0' and X2 = '0' then
  37.                             NextState <= S3;
  38.                       else  NextState <= S2;
  39.                       end if;
  40.          when S3 => if X1 = '0' and X2 = '0' then
  41.                             NextState <= S4;
  42.                       else  NextState <= S3;
  43.                       end if;
  44.          when S4 => if X1 = '0' and X2 = '0' then
  45.                             NextState <= S5;
  46.                       else  NextState <= S4;
  47.                       end if;
  48.          when S5 => if X1 = '0' and X2 = '1' then
  49.                             NextState <= S6;
  50.                       else  NextState <= S5;
  51.                       end if;
  52.          when S6 => if X1 = '1' and X2 = '0' then
  53.                             NextState <= S0;
  54.                       else  NextState <= S6;
  55.                       end if;
  56.    end case;
  57. end process;
  58.  
  59. -- ВЫРАБОТКА ВЫХОДНЫХ СИГНАЛОВ-------------------------------------
  60. process(State)
  61. begin
  62.     case State is
  63.          when S0 => C1 <= '0'; C2 <= '0'; C3 <= '0';
  64.          when S1 => C1 <= '1'; C2 <= '0'; C3 <= '0';
  65.          when S2 => C1 <= '1'; C2 <= '0'; C3 <= '0';
  66.          when S3 => C1 <= '1'; C2 <= '0'; C3 <= '0';
  67.          when S4 => C1 <= '1'; C2 <= '0'; C3 <= '0';
  68.          when S5 => C1 <= '1'; C2 <= '1'; C3 <= '0';
  69.          when S6 => C1 <= '0'; C2 <= '0'; C3 <= '1';
  70.      end case;
  71. end process;
  72. end Behavioral;
  73.  
  74.  
  75. library IEEE;  
  76. use IEEE.STD_LOGIC_1164.ALL;
  77.  
  78. entity RS_Trigger is   -- АНТИДРЕБЕЗГОВЫЙ УЗЕЛ
  79.    Port (S, R: in STD_LOGIC; Q: out STD_LOGIC);
  80. end RS_Trigger;
  81.  
  82. architecture BHV of RS_Trigger is
  83. begin
  84. process (R, S)
  85.    begin
  86.        if (R = '1') and (S = '0') then Q <= '1';
  87.         elsif (R = '0') and (S = '1') then Q <= '0';
  88.       end if;
  89.    end process;
  90. end BHV;
  91.  
  92.  
  93. library IEEE;
  94. use IEEE.STD_LOGIC_1164.ALL;
  95.  
  96. entity Lab3_test is
  97. Port (
  98. CLK1, CLK2, X1, X2: in STD_LOGIC;
  99. C1, C2, C3: out STD_LOGIC);
  100. end Lab3_test;
  101.  
  102. architecture BHV_test of Lab3_test is
  103. signal CLK: STD_LOGIC;
  104.  
  105. component RS_Trigger is
  106. Port (
  107. S, R: in STD_LOGIC; Q: out STD_LOGIC);
  108. end component;
  109.  
  110. component Lab5 is
  111. Port (CLK, X1, X2: in STD_LOGIC;
  112.       C1, C2, C3: out STD_LOGIC);
  113. end component;
  114.  
  115. begin
  116. comp1: RS_Trigger port map(S => CLK1, R => CLK2, Q => CLK);
  117. comp2: Lab5 port map(CLK => CLK, X1 => X1, X2 => X2, C1 => C1, C2 => C2, C3 => C3);
  118. end BHV_test;
  119.  
  120.  
  121.  
  122. library IEEE;
  123. use IEEE.STD_LOGIC_1164.ALL;
  124.  
  125. entity lab3_TB is
  126. end lab3_TB;
  127.  
  128. architecture Behavioral of lab3_TB is
  129. signal CLK1 : STD_LOGIC;
  130. signal CLK2 : STD_LOGIC;
  131. signal X1 : STD_LOGIC;
  132. signal X2 : STD_LOGIC;
  133. signal C1 : STD_LOGIC;
  134. signal C2 : STD_LOGIC;
  135. signal C3 : STD_LOGIC;
  136. component Lab3_test is
  137. Port (
  138. CLK1, CLK2, X1, X2: in STD_LOGIC;
  139. C1, C2, C3: out STD_LOGIC);
  140. end component;
  141.  
  142. begin
  143.  
  144. test_lab3: Lab3_test port map(CLK1 => CLK1, CLK2 => CLK2, X1 => X1,X2 => X2,C1 => C1,C2 => C2,C3 => C3);
  145.  
  146. gen: process
  147. begin
  148. CLK1 <= '0';CLK2 <= '1';
  149. wait for 25 ns;
  150. CLK1 <= '1';CLK2 <= '0';
  151. wait for 25 ns;
  152. end process;
  153.  
  154. test: process
  155. variable i: natural;
  156. begin
  157. wait for 100 ns;
  158. wait until falling_edge(CLK2);
  159. X1 <= '1';
  160. wait until falling_edge(CLK2);
  161. X1 <= '0';X2 <= '1';
  162. for i in 1 to 2 loop
  163. wait until falling_edge(CLK2);
  164. end loop;
  165. X1 <= '0';X2 <= '0';
  166. for i in 1 to 2 loop
  167. wait until falling_edge(CLK2);
  168. end loop;
  169. X1 <= '0';X2 <= '0';
  170. for i in 1 to 2 loop
  171. wait until falling_edge(CLK2);
  172. end loop;
  173. X1 <= '0';X2 <= '0';
  174. for i in 1 to 2 loop
  175. wait until falling_edge(CLK2);
  176. end loop;
  177. X1 <= '0';X2 <= '1';
  178. for i in 1 to 2 loop
  179. wait until falling_edge(CLK2);
  180. end loop;
  181. X1 <= '1';X2 <= '0';
  182. for i in 1 to 2 loop
  183. wait until falling_edge(CLK2);
  184. end loop;
  185. end process;
  186. end Behavioral;
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