library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Lab5 is
Port (CLK, X1, X2: in STD_LOGIC;
      C1, C2, C3: out STD_LOGIC);
end Lab5;

architecture Behavioral of Lab5 is
type FSM_State is(S0, S1, S2, S3, S4, S5, S6);
signal State, NextState: FSM_State;
begin
--ниже  ПАМЯТЬ АВТОМАТА ---------------------------------------
process(CLK)
   begin
     if rising_edge(CLK) then
     if X1 = '1' then
        State <= S0;
     else
        State <= NextState;
end if;
end if;
end process;

--ниже  комбинационная часть АВТОМАТА-вычисление его будущего состояния
process(State, X1, X2)
 begin
   case State is
         when S0 => if X1 = '0' and X2 = '1' then
                            NextState <= S1;
                      else  NextState <= S0;
                      end if;
         when S1 => if X1 = '0' and X2 = '0' then
                            NextState <= S2;
                      else  NextState <= S1;
                      end if;
         when S2 => if X1 = '0' and X2 = '0' then
                            NextState <= S3;
                      else  NextState <= S2;
                      end if;
         when S3 => if X1 = '0' and X2 = '0' then
                            NextState <= S4;
                      else  NextState <= S3;
                      end if;
         when S4 => if X1 = '0' and X2 = '0' then
                            NextState <= S5;
                      else  NextState <= S4;
                      end if;
         when S5 => if X1 = '0' and X2 = '1' then
                            NextState <= S6;
                      else  NextState <= S5;
                      end if;
         when S6 => if X1 = '1' and X2 = '0' then
                            NextState <= S0;
                      else  NextState <= S6;
                      end if;
   end case;
end process;

-- ВЫРАБОТКА ВЫХОДНЫХ СИГНАЛОВ-------------------------------------
process(State)
begin
    case State is
         when S0 => C1 <= '0'; C2 <= '0'; C3 <= '0';
         when S1 => C1 <= '1'; C2 <= '0'; C3 <= '0';
         when S2 => C1 <= '1'; C2 <= '0'; C3 <= '0';
         when S3 => C1 <= '1'; C2 <= '0'; C3 <= '0';
         when S4 => C1 <= '1'; C2 <= '0'; C3 <= '0';
         when S5 => C1 <= '1'; C2 <= '1'; C3 <= '0';
         when S6 => C1 <= '0'; C2 <= '0'; C3 <= '1';
     end case;
end process;
end Behavioral;


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity RS_Trigger is   -- АНТИДРЕБЕЗГОВЫЙ УЗЕЛ
   Port (S, R: in STD_LOGIC; Q: out STD_LOGIC);
end RS_Trigger;

architecture BHV of RS_Trigger is
begin
process (R, S)
   begin
       if (R = '1') and (S = '0') then Q <= '1';
        elsif (R = '0') and (S = '1') then Q <= '0';
      end if;
   end process;
end BHV;


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Lab3_test is
Port (
CLK1, CLK2, X1, X2: in STD_LOGIC;
C1, C2, C3: out STD_LOGIC);
end Lab3_test;

architecture BHV_test of Lab3_test is
signal CLK: STD_LOGIC;

component RS_Trigger is
Port (
S, R: in STD_LOGIC; Q: out STD_LOGIC);
end component;

component Lab5 is
Port (CLK, X1, X2: in STD_LOGIC;
      C1, C2, C3: out STD_LOGIC);
end component;

begin
comp1: RS_Trigger port map(S => CLK1, R => CLK2, Q => CLK);
comp2: Lab5 port map(CLK => CLK, X1 => X1, X2 => X2, C1 => C1, C2 => C2, C3 => C3);
end BHV_test;



library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity lab3_TB is
end lab3_TB;

architecture Behavioral of lab3_TB is
signal CLK1 : STD_LOGIC;
signal CLK2 : STD_LOGIC;
signal X1 : STD_LOGIC;
signal X2 : STD_LOGIC;
signal C1 : STD_LOGIC;
signal C2 : STD_LOGIC;
signal C3 : STD_LOGIC;
component Lab3_test is
Port (
CLK1, CLK2, X1, X2: in STD_LOGIC;
C1, C2, C3: out STD_LOGIC);
end component;

begin

test_lab3: Lab3_test port map(CLK1 => CLK1, CLK2 => CLK2, X1 => X1,X2 => X2,C1 => C1,C2 => C2,C3 => C3);

gen: process
begin
CLK1 <= '0';CLK2 <= '1';
wait for 25 ns;
CLK1 <= '1';CLK2 <= '0';
wait for 25 ns;
end process;

test: process
variable i: natural;
begin
wait for 100 ns;
wait until falling_edge(CLK2);
X1 <= '1';
wait until falling_edge(CLK2);
X1 <= '0';X2 <= '1';
for i in 1 to 2 loop
wait until falling_edge(CLK2);
end loop;
X1 <= '0';X2 <= '0';
for i in 1 to 2 loop
wait until falling_edge(CLK2);
end loop;
X1 <= '0';X2 <= '0';
for i in 1 to 2 loop
wait until falling_edge(CLK2);
end loop;
X1 <= '0';X2 <= '0';
for i in 1 to 2 loop
wait until falling_edge(CLK2);
end loop;
X1 <= '0';X2 <= '1';
for i in 1 to 2 loop
wait until falling_edge(CLK2);
end loop;
X1 <= '1';X2 <= '0';
for i in 1 to 2 loop
wait until falling_edge(CLK2);
end loop;
end process;
end Behavioral;