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Mark_Nagaev Sep 4th, 2018 318 Never
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  1. /*
  2.  * spi-mt7621.c -- MediaTek MT7621 SPI controller driver
  3.  *
  4.  * Copyright (C) 2011 Sergiy <piratfm@gmail.com>
  5.  * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
  6.  * Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name>
  7.  * Copyright (C) 2017 Wim Dumon <wim@emweb.be>
  8.  *
  9.  * Some parts are based on spi-orion.c:
  10.  *   Author: Shadi Ammouri <shadi@marvell.com>
  11.  *   Copyright (C) 2007-2008 Marvell Ltd.
  12.  *
  13.  * This program is free software; you can redistribute it and/or modify
  14.  * it under the terms of the GNU General Public License version 2 as
  15.  * published by the Free Software Foundation.
  16.  */
  17.  
  18.  
  19. #include <linux/init.h>
  20. #include <linux/module.h>
  21. #include <linux/clk.h>
  22. #include <linux/err.h>
  23. #include <linux/delay.h>
  24. #include <linux/io.h>
  25. #include <linux/reset.h>
  26. #include <linux/spi/spi.h>
  27. #include <linux/of_device.h>
  28. #include <linux/platform_device.h>
  29. #include <linux/swab.h>
  30. #include <linux/gpio.h>
  31.  
  32. #include <ralink_regs.h>
  33.  
  34. #undef dev_dbg
  35. //#define dev_dbg dev_info
  36. #define dev_dbg(...)
  37.  
  38. #define SPI_BPW_MASK(bits) BIT((bits) - 1)
  39.  
  40. #define DRIVER_NAME         "spi-mt7621"
  41. /* in msec */
  42. #define RALINK_SPI_WAIT_TIMEOUT 8
  43.  
  44. /* SPISTAT register bit field */
  45. #define SPISTAT_BUSY            BIT(0)
  46.  
  47. #define MT7621_SPI_TRANS    0x00
  48. #define SPITRANS_BUSY       BIT(16)
  49.  
  50. #define MT7621_SPI_OPCODE   0x04
  51. #define MT7621_SPI_DATA0    0x08
  52. #define MT7621_SPI_DATA1    0x0C
  53. #define MT7621_SPI_DATA2    0x10
  54. #define MT7621_SPI_DATA3    0x14
  55. #define MT7621_SPI_DATA4    0x18
  56. #define MT7621_SPI_DATA5    0x1C
  57. #define MT7621_SPI_DATA6    0x20
  58. #define MT7621_SPI_DATA7    0x24
  59. #define SPI_CTL_TX_RX_CNT_MASK  0xff
  60. #define SPI_CTL_START       BIT(8)
  61.  
  62. #define MT7621_SPI_POLAR    0x38
  63. #define MT7621_SPI_MASTER   0x28
  64. #define MT7621_SPI_MOREBUF  0x2c
  65. #define MT7621_SPI_SPACE    0x3c
  66.  
  67. #define MT7621_CPHA     BIT(5)
  68. #define MT7621_CPOL     BIT(4)
  69. #define MT7621_LSB_FIRST    BIT(3)
  70.  
  71. #define RT2880_SPI_MODE_BITS    (SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH)
  72.  
  73. struct mt7621_spi;
  74.  
  75. struct mt7621_spi {
  76.     struct spi_master   *master;
  77.     void __iomem        *base;
  78.     unsigned int        sys_freq;
  79.     unsigned int        speed;
  80.     struct clk      *clk;
  81.     spinlock_t      lock;
  82.  
  83.     struct mt7621_spi_ops   *ops;
  84. };
  85.  
  86. static inline struct mt7621_spi *spidev_to_mt7621_spi(struct spi_device *spi)
  87. {
  88.     return spi_master_get_devdata(spi->master);
  89. }
  90.  
  91. static inline u32 mt7621_spi_read(struct mt7621_spi *rs, u32 reg)
  92. {
  93.     return ioread32(rs->base + reg);
  94. }
  95.  
  96. static inline void mt7621_spi_write(struct mt7621_spi *rs, u32 reg, u32 val)
  97. {
  98.     iowrite32(val, rs->base + reg);
  99. }
  100.  
  101. static void mt7621_spi_reg_dump(struct mt7621_spi *rs)
  102. {
  103.     dev_dbg(&rs->master->dev, "SPI_OP_ADDR: %08x\n", mt7621_spi_read(rs, MT7621_SPI_OPCODE));
  104.     dev_dbg(&rs->master->dev, "SPI_DIDO: %08x %08x %08x %08x\n",
  105.         mt7621_spi_read(rs, MT7621_SPI_DATA0),
  106.         mt7621_spi_read(rs, MT7621_SPI_DATA1),
  107.         mt7621_spi_read(rs, MT7621_SPI_DATA2),
  108.         mt7621_spi_read(rs, MT7621_SPI_DATA3));
  109.     dev_dbg(&rs->master->dev, "SPI_DIDO: %08x %08x %08x %08x\n",
  110.         mt7621_spi_read(rs, MT7621_SPI_DATA4),
  111.         mt7621_spi_read(rs, MT7621_SPI_DATA5),
  112.         mt7621_spi_read(rs, MT7621_SPI_DATA6),
  113.         mt7621_spi_read(rs, MT7621_SPI_DATA7));
  114.     dev_dbg(&rs->master->dev, "SPI_MASTER: %08x\n", mt7621_spi_read(rs, MT7621_SPI_MASTER));
  115.     dev_dbg(&rs->master->dev, "SPI_MORE_BUF: %08x\n", mt7621_spi_read(rs, MT7621_SPI_MOREBUF));
  116. }
  117.  
  118. static void mt7621_spi_set_cs(struct spi_device *spi, bool enable)
  119. {
  120.     struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
  121.  
  122.  
  123.     u32 polar = 0;
  124.     int cs = spi->chip_select;
  125.  
  126.     dev_dbg(&spi->dev, "set CS %d, enable %d\n", cs, (int)enable);
  127.  
  128.     if (cs > 7) {
  129.         dev_err(&spi->dev, "CS > 7 not supported\n");
  130.     } else {
  131.         if (!enable)
  132.             polar = BIT(cs);
  133.     }
  134.     mt7621_spi_write(rs, MT7621_SPI_POLAR, polar);
  135. }
  136.  
  137. static int mt7621_spi_prepare(struct spi_device *spi, unsigned int speed)
  138. {
  139.     struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
  140.     u32 rate;
  141.     u32 reg;
  142.  
  143.     dev_dbg(&spi->dev, "speed:%u\n", speed);
  144.  
  145.     rate = DIV_ROUND_UP(rs->sys_freq, speed);
  146.     // can't reach highest speed if max frequency happens to be odd
  147.     // due to rounding errors
  148.     if (speed == spi->master->max_speed_hz)
  149.         rate = 2;
  150.  
  151.     dev_dbg(&spi->dev, "rate-1:%u\n", rate);
  152.  
  153.     if (rate > 4097)
  154.         return -EINVAL;
  155.  
  156.     if (rate < 2)
  157.         rate = 2;
  158.     rs->speed = rs->sys_freq / rate;
  159.  
  160.     //rate = 4;
  161.  
  162.     //rate = 50; // FIXME!! remove me
  163.  
  164.     reg = mt7621_spi_read(rs, MT7621_SPI_MASTER);
  165.  
  166.     // CS strategy: preferably use GPIO CS exlusively, the system is
  167.     // more flexible. We're not really using the HW mechanism to set
  168.     // CS0/CS1 anyway, but are effectively setting then manually (like
  169.     // GPIOs) by togling the CS polarity while they are in idle state.
  170.     // To this purpose, CS7 is always selected as the CS to use, and
  171.     // the polarity register is modified when CS needs to be toggled.
  172.     reg |= 7 << 29;
  173.  
  174.     // always use more_buf mode
  175.     reg |= 1 << 2;
  176.  
  177.     // full duplex does not work reliably
  178.     reg &= ~(1 << 10);
  179.  
  180.     // set clock speed
  181.     reg &= ~(0xfff << 16);
  182.     reg |= (rate - 2) << 16;
  183.  
  184.     reg &= ~MT7621_LSB_FIRST;
  185.     if (spi->mode & SPI_LSB_FIRST)
  186.         reg |= MT7621_LSB_FIRST;
  187.  
  188.     reg &= ~(MT7621_CPHA | MT7621_CPOL);
  189.     switch(spi->mode & (SPI_CPOL | SPI_CPHA)) {
  190.         case SPI_MODE_0:
  191.             break;
  192.         case SPI_MODE_1:
  193.             reg |= MT7621_CPHA;
  194.             break;
  195.         case SPI_MODE_2:
  196.             reg |= MT7621_CPOL;
  197.             break;
  198.         case SPI_MODE_3:
  199.             reg |= MT7621_CPOL | MT7621_CPHA;
  200.             break;
  201.     }
  202.     mt7621_spi_write(rs, MT7621_SPI_MASTER, reg);
  203.  
  204.     return 0;
  205. }
  206.  
  207. static inline int mt7621_spi_wait_till_ready(struct spi_device *spi)
  208. {
  209.     struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
  210.  
  211.     unsigned long deadline = jiffies + msecs_to_jiffies(RALINK_SPI_WAIT_TIMEOUT);
  212.     while (time_before(jiffies, deadline)) {
  213.         u32 status;
  214.         status = mt7621_spi_read(rs, MT7621_SPI_TRANS);
  215.         if ((status & SPITRANS_BUSY) == 0) {
  216.             return 0;
  217.         }
  218.         cpu_relax();
  219.     }
  220.  
  221.     return -ETIMEDOUT;
  222. }
  223.  
  224.  
  225. // returns amount of bytes transfered
  226. static int mt7621_spi_transfer_chunk(struct spi_master *master,
  227.                    struct spi_device *spi,
  228.                    struct spi_transfer *t,
  229.                    int offset)
  230. {
  231.     u32 data[9] = {0};
  232.     u32 val;
  233.     int i;
  234.     struct mt7621_spi *rs = spi_master_get_devdata(master);
  235.     int len = t->len - offset;
  236.  
  237.     dev_dbg(&spi->dev, "chunk: offset=%d, len=%d\n", offset, len);
  238.  
  239.     if (t->rx_buf) {
  240.         // RX bytes are stored in DIDO registers. So max number of
  241.         // bytes to RX is 8 * 4 = 32
  242.         if (len > 32)
  243.             len = 32;
  244.         val = (len * 8) << 12;
  245.         mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val);
  246.         dev_dbg(&spi->dev, "Wrote %08x to MOREBUF\n", val);
  247.     }
  248.     if (t->tx_buf) {
  249.         const unsigned char *buf = t->tx_buf;
  250.         // First 4 bytes to TX are stored in opcode register,
  251.         // rest of TX bytes are stored in DIDO registers. So
  252.         // max number of bytes to TX is (1 + 8) * 4 = 36.
  253.         if (len > 36)
  254.             len = 36;
  255.  
  256.         val = (min_t(int, len, 4) * 8) << 24;
  257.         if (len > 4)
  258.             val |= (len - 4) * 8;
  259.         mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val);
  260.         dev_dbg(&spi->dev, "Wrote %08x to MOREBUF\n", val);
  261.  
  262.         dev_dbg(&spi->dev, "copying TX buf (%02x)\n", (int)buf[offset]);
  263.         // FIXME: silly copy?
  264.         for (i = 0; i < len; i++)
  265.             data[i / 4] |= buf[i + offset] << (8 * (i & 3));
  266.  
  267.         data[0] = swab32(data[0]);
  268.         if (len < 4)
  269.             data[0] >>= (4 - len) * 8;
  270.  
  271.         for (i = 0; i < 9; i++)
  272.             mt7621_spi_write(rs, MT7621_SPI_OPCODE + i * 4, data[i]);
  273.     }
  274.  
  275.  
  276.     dev_dbg(&spi->dev, "initializing transfer\n");
  277.     mt7621_spi_reg_dump(rs);
  278.     val = mt7621_spi_read(rs, MT7621_SPI_TRANS);
  279.     val |= SPI_CTL_START;
  280.     mt7621_spi_write(rs, MT7621_SPI_TRANS, val);
  281.  
  282.     // Ideally use an interrupt here iso busy waiting, if clock is slow
  283.     mt7621_spi_wait_till_ready(spi);
  284.     mt7621_spi_reg_dump(rs);
  285.  
  286.     if (t->rx_buf) {
  287.         unsigned char *buf = t->rx_buf;
  288.         dev_dbg(&spi->dev, "writing RX buf\n");
  289.         for (i = 0; i < 9; i++)
  290.             data[i] = mt7621_spi_read(rs, MT7621_SPI_DATA0 + i * 4);
  291.         for (i = 0; i < len; i++)
  292.             buf[i + offset] = data[i / 4] >> (8 * (i & 3));
  293.     }
  294.     return len;
  295. }
  296.  
  297. static int mt7621_spi_transfer_half_duplex(struct spi_master *master,
  298.                        struct spi_device *spi,
  299.                        struct spi_transfer *t)
  300. {
  301.     int status = 0;
  302.     int offset = 0;
  303.     unsigned int speed = spi->max_speed_hz;
  304.  
  305.     mt7621_spi_wait_till_ready(spi);
  306.  
  307.     if (t->speed_hz < speed)
  308.         speed = t->speed_hz;
  309.  
  310.     if (t->rx_buf && t->tx_buf) {
  311.         // MT7688 has a HW bug, causing the second bit of the first RX
  312.         // byte of a full-duplex SPI transfer to be corrupted in
  313.         // some cases
  314.         dev_err(&spi->dev, "full duplex not supported\n");
  315.         status = -EIO;
  316.         goto msg_done;
  317.     }
  318.  
  319.     if (mt7621_spi_prepare(spi, speed)) {
  320.         dev_dbg(&spi->dev, "mt7621_spi_prepare failed\n");
  321.         status = -EIO;
  322.         goto msg_done;
  323.     }
  324.  
  325.     while (offset < t->len)
  326.         offset += mt7621_spi_transfer_chunk(master, spi, t, offset);
  327.  
  328. msg_done:
  329.     spi_finalize_current_transfer(master);
  330.  
  331.     return status;
  332. }
  333.  
  334.  
  335. static int mt7621_spi_transfer_one(struct spi_master *master,
  336.                    struct spi_device *spi,
  337.                    struct spi_transfer *t)
  338. {
  339.     return mt7621_spi_transfer_half_duplex(master, spi, t);
  340. }
  341.  
  342. static int mt7621_spi_setup(struct spi_device *spi)
  343. {
  344.     int ret = 0;
  345.     gpio_free(spi->cs_gpio);
  346.     if (spi->cs_gpio != -ENOENT) {
  347.         ret = gpio_is_valid(spi->cs_gpio);
  348.         if (!ret) {
  349.             dev_err(&spi->dev, "gpio cs %d not valid\n",
  350.                 spi->cs_gpio);
  351.             ret = -ENOENT;
  352.             goto exit;
  353.         }
  354.         ret = gpio_request(spi->cs_gpio, DRIVER_NAME);
  355.         if (ret) {
  356.             dev_err(&spi->dev, "failed to request gpio cs %d\n",
  357.                 spi->cs_gpio);
  358.             goto exit;
  359.         }
  360.         ret = gpio_direction_output(spi->cs_gpio,
  361.                         !(spi->mode & SPI_CS_HIGH));
  362.         if (ret) {
  363.             dev_err(&spi->dev,
  364.                 "Failed to set gpio cs %d as output\n",
  365.                 spi->cs_gpio);
  366.             goto exit;
  367.         }
  368.     }
  369. exit:
  370.     return ret;
  371.  
  372. }
  373.  
  374. static int mt7621_spi_cleanup(struct spi_device *spi)
  375. {
  376.     if(gpio_is_valid(spi->cs_gpio)) {
  377.         gpio_free(spi->cs_gpio);
  378.     }
  379. }
  380.  
  381. static const struct of_device_id mt7621_spi_match[] = {
  382.     { .compatible = "ralink,mt7621-spi" },
  383.     {},
  384. };
  385. MODULE_DEVICE_TABLE(of, mt7621_spi_match);
  386.  
  387. static int mt7621_spi_probe(struct platform_device *pdev)
  388. {
  389.     const struct of_device_id *match;
  390.     struct spi_master *master;
  391.     struct mt7621_spi *rs;
  392.     unsigned long flags;
  393.     void __iomem *base;
  394.     struct resource *r;
  395.     int status = 0;
  396.     struct clk *clk;
  397.     int sys_freq;
  398.     struct mt7621_spi_ops *ops;
  399.  
  400.     match = of_match_device(mt7621_spi_match, &pdev->dev);
  401.     if (!match)
  402.         return -EINVAL;
  403.     ops = (struct mt7621_spi_ops *)match->data;
  404.  
  405.     r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  406.     base = devm_ioremap_resource(&pdev->dev, r);
  407.     if (IS_ERR(base))
  408.         return PTR_ERR(base);
  409.  
  410.     clk = devm_clk_get(&pdev->dev, NULL);
  411.     if (IS_ERR(clk)) {
  412.         dev_err(&pdev->dev, "unable to get SYS clock, err=%d\n",
  413.             status);
  414.         return PTR_ERR(clk);
  415.     }
  416.  
  417.     status = clk_prepare_enable(clk);
  418.     if (status)
  419.         return status;
  420.     sys_freq = clk_get_rate(clk);
  421.  
  422.     master = spi_alloc_master(&pdev->dev, sizeof(*rs));
  423.     if (master == NULL) {
  424.         dev_info(&pdev->dev, "master allocation failed\n");
  425.         return -ENOMEM;
  426.     }
  427.  
  428.     master->mode_bits = RT2880_SPI_MODE_BITS;
  429.  
  430.     master->setup = mt7621_spi_setup;
  431.     master->transfer_one = mt7621_spi_transfer_one;
  432.     master->bits_per_word_mask = SPI_BPW_MASK(8);
  433.     master->dev.of_node = pdev->dev.of_node;
  434.     master->num_chipselect = 64;
  435.     master->flags = SPI_MASTER_HALF_DUPLEX;
  436.     master->set_cs = mt7621_spi_set_cs;
  437.     master->max_speed_hz = sys_freq / 2;
  438.     master->min_speed_hz = sys_freq / 4097;
  439.  
  440.     dev_set_drvdata(&pdev->dev, master);
  441.  
  442.     rs = spi_master_get_devdata(master);
  443.     rs->base = base;
  444.     rs->clk = clk;
  445.     rs->master = master;
  446.     rs->sys_freq = sys_freq;
  447.     rs->ops = ops;
  448.     dev_info(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
  449.     spin_lock_irqsave(&rs->lock, flags);
  450.  
  451.     device_reset(&pdev->dev);
  452.  
  453.     return spi_register_master(master);
  454. }
  455.  
  456. static int mt7621_spi_remove(struct platform_device *pdev)
  457. {
  458.     struct spi_master *master;
  459.     struct mt7621_spi *rs;
  460.  
  461.     master = dev_get_drvdata(&pdev->dev);
  462.     rs = spi_master_get_devdata(master);
  463.  
  464.     clk_disable(rs->clk);
  465.     spi_unregister_master(master);
  466.  
  467.     return 0;
  468. }
  469.  
  470. MODULE_ALIAS("platform:" DRIVER_NAME);
  471.  
  472. static struct platform_driver mt7621_spi_driver = {
  473.     .driver = {
  474.         .name = DRIVER_NAME,
  475.         .owner = THIS_MODULE,
  476.         .of_match_table = mt7621_spi_match,
  477.     },
  478.     .probe = mt7621_spi_probe,
  479.     .remove = mt7621_spi_remove,
  480. };
  481.  
  482. module_platform_driver(mt7621_spi_driver);
  483.  
  484. MODULE_DESCRIPTION("MT7621 SPI driver");
  485. MODULE_AUTHOR("Felix Fietkau <nbd@nbd.name>");
  486. MODULE_LICENSE("GPL");
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