library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.bspline_pckg.all;

entity farrow is

    generic(
            Wi : natural;
            Wa : natural;
            Wc : natural;
            Wm : natural;
            Wo : natural
            );
    port(
        clk : in std_logic;
        rst : in std_logic;
        mu  : in signed(Wm-1 downto 0);
        data_in  : in signed(Wi-1 downto 0);
        data_out : out signed(Wo-1 downto 0)
        );

end entity;

architecture rtl of farrow is

    constant zeros : signed(Wa-Wi-1 downto 0) := (others => '0');

    signal reg : t_reg_f(0 to 21);
    signal data_in_se : signed(Wa-1 downto 0);
    signal farrow_coeffs : t_coeffs_f  := ("000101010101010101","010101010101010101");

begin

    --------------------------------------
    ----------- sign extension -----------
    --------------------------------------
    data_in_se <= resize(data_in, Wa);

    --------------------------------------
    ----------- delay registers ----------
    --------------------------------------
    process(clk) is
    begin
        if rising_edge(clk) then
            if rst = '1' then
                reg(0) <= (others => '0');
            else
                reg(0) <= data_in_se;
            end if;
        end if;
    end process;

    process(clk) is
    begin
        if rising_edge(clk) then
            if rst = '1' then
                reg(1) <= (others => '0');
            else
                reg(1) <= reg(0);
            end if;
        end if;
    end process;

    process(clk) is
    begin
        if rising_edge(clk) then
            if rst = '1' then
                reg(2) <= (others => '0');
            else
                reg(2) <= reg(1);
            end if;
        end if;
    end process;

    --------------------------------------
    ------------ C3(z) filter ------------
    --------------------------------------
    pmr_1:
    component preadd_mult_round
        generic map(
                    Wa => Wa,
                    Wb => Wa,
                    Wc => Wc,
                    Wo => Wa,
                    round_mode => round_mode
                    )
        port map(
                clk => clk,
                rst => rst,
                addsub => '0',
                a => data_in_se,
                b => reg(2),
                c => farrow_coeffs(0),
                p => reg(3)
                );

    ps_1:
    component preadd_shift
        generic map(
                    S => 1,
                    Wa => Wa
                    )
        port map(
                clk => clk,
                rst => rst,
                addsub => '0',
                a => reg(1),
                b => reg(0),
                p => reg(4)
                );

    vd_1:
    component var_delay
        generic map(
                    D => 1,
                    Wa => Wa
                    )
        port map(
                clk => clk,
                rst => rst,
                data_in  => reg(4),
                data_out => reg(5)
                );

    process(clk) is
    begin
        if rising_edge(clk) then
            if rst = '1' then
                reg(6) <= (others => '0');
            else
                reg(6) <= reg(3) + reg(5);      -- v3(n)
            end if;
        end if;
    end process;

    --------------------------------------
    ------------ C2(z) filter ------------
    --------------------------------------
    ps_2:
    component preadd_shift
        generic map(
                    S => 1,
                    Wa => Wa
                    )
        port map(
                clk => clk,
                rst => rst,
                addsub => '1',
                a => reg(0),
                b => reg(2),
                p => reg(7)
                );

    vd_2:
    component var_delay
        generic map(
                    D => 2,
                    Wa => Wa
                    )
        port map(
                clk => clk,
                rst => rst,
                data_in  => reg(1),
                data_out => reg(8)
                );

    process(clk) is
    begin
        if rising_edge(clk) then
            if rst = '1' then
                reg(9) <= (others => '0');
            else
                reg(9) <= reg(7) - reg(8);
            end if;
        end if;
    end process;

    vd_3:
    component var_delay
        generic map(
                    D => 1,
                    Wa => Wa
                    )
        port map(
                clk => clk,
                rst => rst,
                data_in  => reg(9),
                data_out => reg(10)     -- v2(n)
                );

    --------------------------------------
    ------------ C1(z) filter ------------
    --------------------------------------
    ps_3:
    component preadd_shift
        generic map(
                    S => 1,
                    Wa => Wa
                    )
        port map(
                clk => clk,
                rst => rst,
                addsub => '0',
                a => reg(0),
                b => reg(2),
                p => reg(11)
                );

    vd_4:
    component var_delay
        generic map(
                    D => 2,
                    Wa => Wa
                    )
        port map(
                clk => clk,
                rst => rst,
                data_in  => reg(11),
                data_out => reg(12)     -- v1(n)
                );

    --------------------------------------
    ------------ C0(z) filter ------------
    --------------------------------------
    pmr_2:
    component preadd_mult_round
        generic map(
                    Wa => Wa,
                    Wb => Wa,
                    Wc => Wc,
                    Wo => Wa,
                    round_mode => round_mode
                    )
        port map(
                clk => clk,
                rst => rst,
                addsub => '1',
                a => reg(0),
                b => reg(2),
                c => farrow_coeffs(0),
                p => reg(13)
                );

    mr_1:
    component mult_round
        generic map(
                    Wa => Wa,
                    Wb => Wa,
                    Wo => Wa,
                    round_mode => round_mode

                    )
        port map(
                clk => clk,
                rst => rst,
                a => reg(1),
                b => farrow_coeffs(1),
                p => reg(14)
                );

    vd_5:
    component var_delay
        generic map(
                    D => 1,
                    Wa => Wa
                    )
        port map(
                clk => clk,
                rst => rst,
                data_in  => reg(14),
                data_out => reg(15)
                );

    process(clk) is
    begin
        if rising_edge(clk) then
            if rst = '1' then
                reg(16) <= (others => '0');
            else
                reg(16) <= reg(13) + reg(15);   -- v0[n]
            end if;
        end if;
    end process;

    --------------------------------------
    ----------- Horner's rule ------------
    --------------------------------------
    vd_6:
    component var_delay
        generic map(
                    D => 3,
                    Wa => Wa
                    )
        port map(
                clk => clk,
                rst => rst,
                data_in  => reg(12),
                data_out => reg(17)
                );

    vd_7:
    component var_delay
        generic map(
                    D => 6,
                    Wa => Wa
                    )
        port map(
                clk => clk,
                rst => rst,
                data_in  => reg(16),
                data_out => reg(18)
                );


    mrp_1:
    component mult_round_postadd
        generic map(
                    Wa => Wa,
                    Wb => Wm,
                    Wo => Wa,
                    round_mode => round_mode
                    )
        port map(
                clk => clk,
                rst => rst,
                addsub => '1',
                a => reg(6),
                b => mu,
                c => reg(10),
                p => reg(19)
                );

    mrp_2:
    component mult_round_postadd
        generic map(
                    Wa => Wa,
                    Wb => Wm,
                    Wo => Wa,
                    round_mode => round_mode
                    )
        port map(
                clk => clk,
                rst => rst,
                addsub => '1',
                a => reg(19),
                b => mu,
                c => reg(17),
                p => reg(20)
                );

    mrp_3:
    component mult_round_postadd
        generic map(
                    Wa => Wa,
                    Wb => Wm,
                    Wo => Wa,
                    round_mode => round_mode
                    )
        port map(
                clk => clk,
                rst => rst,
                addsub => '1',
                a => reg(20),
                b => mu,
                c => reg(18),
                p => reg(21)
                );

    data_out <= reg(21)(Wa-3 downto Wa-Wo-2);

    -- REGs 6, 10, 12, 16 are filter outputs

    -- probe(clk, rst, reg(6), "C:\Users\edavpav\Documents\Diplomski\VHDL\b_spline_rtl\probe_signals\farrow\v3.txt");
    -- probe(clk, rst, reg(10), "C:\Users\edavpav\Documents\Diplomski\VHDL\b_spline_rtl\probe_signals\farrow\v2.txt");
    -- probe(clk, rst, reg(12), "C:\Users\edavpav\Documents\Diplomski\VHDL\b_spline_rtl\probe_signals\farrow\v1.txt");
    -- probe(clk, rst, reg(16), "C:\Users\edavpav\Documents\Diplomski\VHDL\b_spline_rtl\probe_signals\farrow\v0.txt");
    -- probe(clk, rst, reg(19), "C:\Users\edavpav\Documents\Diplomski\VHDL\b_spline_rtl\probe_signals\farrow\h3.txt");
    -- probe(clk, rst, reg(20), "C:\Users\edavpav\Documents\Diplomski\VHDL\b_spline_rtl\probe_signals\farrow\h2.txt");
    -- probe(clk, rst, reg(21), "C:\Users\edavpav\Documents\Diplomski\VHDL\b_spline_rtl\probe_signals\farrow\h1.txt");

end rtl;