SEM_SEQUENCE_GEN

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-- File : sem_driver.vhd
-- Project : ASCP -- Autonomous Semaphore Control Module
-- Creation : 18.7.2019
-- Limitations : none
-- Errors : none known
-- Simulator :
-- Synthesizer :
-- Platform : CentOS7
-- Targets : Simulation, Synthesis, Implementation
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-- Authors : Milan Nedic (minedic)
-- Organization : ELSYS Eastern Europe
-- Email : [email protected]
-- Address : Omladinskih brigada 88b, Belgrade, Serbia/Europe
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-- Copyright Notice
-- This work is licensed under the General Public License (GPL).
--------------------------------------------------------------------------------
-- Function description
-- This module performs generation of select signals for interval counter's
-- input interval routing based on a semaphore phase.
--------------------------------------------------------------------------------
-- Revision History
-- Date        Author     Comments
-- 18.7.2019   minedic    Created
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity sem_sequence_gen is
  generic (
    SEQ_CNTR_WIDTH : integer := 2
    );
  port (

    ----------------------------------------------------------------
    -- Clock and reset
    ----------------------------------------------------------------
    pi_clk   : in std_logic;
    pi_rst_n : in std_logic;

    ----------------------------------------------------------------
    -- Control signals
    ----------------------------------------------------------------
    preload_init_i  : in std_logic;
    step_overflow_i : in std_logic;

    ----------------------------------------------------------------
    -- Selection signals for routing in SEM_DRIVER and INTVL_COUNTER
    ----------------------------------------------------------------
    cnt_intvl_sel_o : out std_logic_vector(SEQ_CNTR_WIDTH-1 downto 0);
    sem_phase_sel_o : out std_logic_vector(SEQ_CNTR_WIDTH-1 downto 0)
    );
end entity;

architecture beh of sem_sequence_gen is

  -- 2-bit counter, always 2 bit wide, generation mux select for
  -- interval routing to the counter register.
  signal seq_cntr_r        : std_logic_vector(SEQ_CNTR_WIDTH-1 downto 0);
  signal seq_cntr_nxt      : std_logic_vector(SEQ_CNTR_WIDTH-1 downto 0);
  signal routed_cntr_val_s : std_logic_vector(SEQ_CNTR_WIDTH-1 downto 0);
  signal sem_phase_sel_s   : std_logic_vector(SEQ_CNTR_WIDTH-1 downto 0);
  signal en_s              : std_logic;
begin

  ------------------------------------------------------------------------------
  -- Sequence counter, selects MUX inputs and routes selected value (01, 10, 11)
  -- to the intvl_counter
  ------------------------------------------------------------------------------
  SEQUENCE_CNTR : process(pi_clk, pi_rst_n, preload_init_i, en_s)
  begin
    if(clk'event and clk = '1') then
      if pi_rst_n = '0' then
        seq_cntr_reg <= (others => '0');
      else
        if en_s = '1' then
          seq_cntr_r <= seq_cntr_nxt;
        end if;
      end if;
    end if;
  end process;

  -- counter's next value
  seq_cntr_nxt <= seq_cntr_r + '1';

  -- sensitive to counter's register output value.
  SEQUENCE_MUX : process(seq_cntr_r)
  begin
    case seq_cntr_r is
      when "00" => sem_phase_sel_s <= "01";
      when "01" => sem_phase_sel_s <= "10";
      when "10" => sem_phase_sel_s <= "11";
      when "11" => sem_phase_sel_s <= "10";
    end case;
  end process;

  -- assign output signal with corresponding internal wire
  sem_phase_sel_o <= sem_phase_sel_s;

  ROUTING_MUXES : process(preload_init_i, sem_phase_sel_s, routed_cntr_val_s,
                          step_overflow_i)
  begin
    -- enable signal router
    case preload_init_i is
      when '0' => en_s <= '1';
      when '1' => en_s <= step_overflow_i;
    end case;

    -- 00 value router, used to select old counter register value
    -- until it generates overflow decrementing earlier selected interval
    case step_overflow_i is
      when '0' => routed_cntr_val_s <= (others => '0');
      when '1' => routed_cntr_val_s <= sem_phase_sel_s;
    end case;

    -- final mux before module boundary, routes counter value to intvl_counter
    case prelod_init_i is
      when '0' => sem_intvl_sel_o <= "01";
      when '1' => sem_intvl_sel_o <= routed_cntr_val_s;
    end case;
  end process;
end beh;