uas_arduino

FSK Generator

Dec 16th, 2014
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  1. library ieee;
  2.  
  3. use ieee.std_logic_1164.all;
  4. use ieee.numeric_std.all;
  5. use work.frame_lib.all;
  6.  
  7. entity fsk is
  8.     port ( clk : in std_logic;
  9.            rst : in std_logic;
  10.            sine_out : out std_logic_vector(7 downto 0);
  11.            leds : out std_logic_vector(7 downto 0);
  12.            rx : in std_logic);
  13. end fsk;
  14.  
  15. architecture behave of fsk is
  16.  
  17.     signal new_frame, last_new_frame : std_logic;
  18.     signal frame : frame_t;
  19.     COMPONENT uart_comms_generic
  20.         GENERIC(
  21.             clk_rate : natural;
  22.             baud_rate: natural
  23.         );
  24.         PORT(
  25.             clk : IN std_logic;
  26.             rst : IN std_logic;
  27.             rx : IN std_logic;          
  28.             frame : OUT frame_t;
  29.             new_frame : OUT std_logic
  30.         );
  31.     END COMPONENT;
  32.  
  33.     type freq_input_type is array(0 to 1) of std_logic_vector(15 downto 0);
  34.     signal pincs : freq_input_type;
  35.  
  36.     type sine_buffer_type is array(0 to 1) of std_logic_vector(sine_out'range);
  37.     signal sine_buffers : sine_buffer_type;
  38.     COMPONENT fsk_dds
  39.         PORT (
  40.                 clk : IN STD_LOGIC;
  41.                 pinc_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
  42.                 sine : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
  43.         );
  44.     END COMPONENT;
  45.  
  46.     signal lfsr : std_logic_vector(19 downto 0) := (others => '1');
  47.     signal lfsr_divider : unsigned(31 downto 0) := (others => '0');
  48.     signal symbol : integer range 0 to 1;
  49.  
  50. begin
  51.     symbol <= 1 when lfsr(0) = '1' else 0;
  52.     sine_out <= std_logic_vector((unsigned(sine_buffers(symbol)) + 127) / 2);
  53.     leds <= lfsr(7 downto 0);
  54.  
  55.     process(clk, rst)
  56.     begin
  57.         if(rst = '1') then
  58.             lfsr <= (others => '1');
  59.             lfsr_divider <= (others => '0');
  60.         elsif(rising_edge(clk)) then
  61.             if(lfsr_divider = 100_000_000 / 25) then
  62.                 lfsr_divider <= (others => '1');
  63.                 lfsr <= lfsr(18 downto 0) & ( lfsr(16) xor lfsr(19) );
  64.             else
  65.                 lfsr_divider <= lfsr_divider + 1;
  66.             end if;
  67.         end if;
  68.     end process;
  69.  
  70.     process(clk, rst)
  71.     begin
  72.         if(rst = '1') then
  73.             last_new_frame <= '0';
  74.             pincs(0) <= (others => '0');
  75.             pincs(1) <= (others => '0');
  76.         elsif(rising_edge(clk)) then
  77.             if(new_frame = '1' and last_new_frame = '0') then
  78.                 case frame(3) is
  79.                     when x"03" =>
  80.                         pincs(1) <= frame(4) & frame(5);
  81.                     when x"04" =>
  82.                         pincs(0) <= frame(4) & frame(5);
  83.                     when others =>
  84.                         null;
  85.                 end case;
  86.             end if;
  87.  
  88.             last_new_frame <= new_frame;
  89.         end if;
  90.     end process;
  91.    
  92.     mark_dds : fsk_dds
  93.     PORT MAP (
  94.             clk => clk,
  95.         pinc_in => pincs(1),
  96.         sine => sine_buffers(1)
  97.     );
  98.  
  99.     space_dds : fsk_dds
  100.     PORT MAP (
  101.             clk => clk,
  102.             pinc_in => pincs(0),
  103.             sine => sine_buffers(0)
  104.     );
  105.  
  106.  
  107.     uart_comms_generic_inst : uart_comms_generic
  108.     GENERIC MAP (
  109.         clk_rate  => 100_000_000,
  110.         baud_rate => 500_000)
  111.     PORT MAP(
  112.         clk => clk,
  113.         rst => rst,
  114.         rx => rx,
  115.         frame => frame,
  116.         new_frame => new_frame
  117.     );
  118.  
  119. end behave;
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