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  1. ----------------------------------------------------------------------------------
  2. -- Company:
  3. -- Engineer:
  4. --
  5. -- Create Date:    11:27:52 06/04/2019
  6. -- Design Name:
  7. -- Module Name:    mux_wybierajacy_cyfre_z_blank - Behavioral
  8. -- Project Name:
  9. -- Target Devices:
  10. -- Tool versions:
  11. -- Description:
  12. --
  13. -- Dependencies:
  14. --
  15. -- Revision:
  16. -- Revision 0.01 - File Created
  17. -- Additional Comments:
  18. --
  19. ----------------------------------------------------------------------------------
  20. library IEEE;
  21. use IEEE.STD_LOGIC_1164.ALL;
  22.  
  23. -- Uncomment the following library declaration if using
  24. -- arithmetic functions with Signed or Unsigned values
  25. --use IEEE.NUMERIC_STD.ALL;
  26.  
  27. -- Uncomment the following library declaration if instantiating
  28. -- any Xilinx primitives in this code.
  29. --library UNISIM;
  30. --use UNISIM.VComponents.all;
  31.  
  32. entity mux_wybierajacy_cyfre_z_blank is
  33.     Port ( switch : in  STD_LOGIC;
  34.            wejscie : in  STD_LOGIC_VECTOR (3 downto 0);
  35.            wyjscie : out  STD_LOGIC_VECTOR (3 downto 0));
  36. end mux_wybierajacy_cyfre_z_blank;
  37.  
  38. architecture Behavioral of mux_wybierajacy_cyfre_z_blank is
  39. signal blank : std_logic_vector(3 downto 0):="1010";
  40.  
  41. begin
  42. with switch select
  43.     wyjscie <= wejscie when '0',
  44.                   blank when others;
  45.                  
  46.  
  47. end Behavioral;
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