Assignment-VHDL

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-- Company:
-- Engineer:
--
-- Create Date:    23:26:17 02/27/2016
-- Design Name:
-- Module Name:    addAndSub - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.std_logic_arith.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity addAndSub is
    Port ( A,B : in  STD_LOGIC_VECTOR (3 downto 0);
           SingA : in  STD_LOGIC;
           SingB : in  STD_LOGIC;
              Operator : in STD_LOGIC;
           C : out  STD_LOGIC_VECTOR (4 downto 0));
end addAndSub;

architecture Behavioral of addAndSub is
    signal x : integer := 0;
begin

    process
        variable AInt, BInt, AB : integer;
    begin
        AInt := conv_integer(A(2 downto 0));
        BInt := conv_integer(B(2 downto 0));

        if A(3) = '1' then AInt := AInt*(-1);
        end if;

        if B(3) = '1' then BInt := BInt*(-1);
        end if;

        AB := AInt + BInt;
        C <= conv_std_logic_vector(AB, 4);
    end process;
end Behavioral;