TP 3 Level 2

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    09:55:25 11/21/2014
-- Design Name:
-- Module Name:    Counter - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Counter is
    Port ( Reset : in  STD_LOGIC;
           CLK : in  STD_LOGIC;
           S : out  STD_LOGIC_VECTOR(25 downto 0));
end Counter;

architecture Behavioral of Counter is

signal Add : STD_LOGIC_VECTOR(25 downto 0);
signal Reg : STD_LOGIC_VECTOR(25 downto 0);
signal Mux : STD_LOGIC_VECTOR(25 downto 0);
signal Cmp : STD_LOGIC;

begin

Reg <= "00000000000000000000000000" when Reset = '0' else Mux when rising_edge(CLK);

Add <= Reg + "0000000000000000000000001";

Mux <= Add when Cmp = '0' else "00000000000000000000000000" when Cmp = '1';

Cmp <= '1' when Add > "0000000000000000000001000" else '0';

S <= Mux;

end Behavioral;