calosc

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-- Company:
-- Engineer:
--
-- Create Date:    13:06:52 05/25/2016
-- Design Name:
-- Module Name:    multiplekser - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity multiplekser is
    Port ( segCode : inout  STD_LOGIC_VECTOR (7 downto 0);
           segLine : inout  STD_LOGIC_VECTOR (3 downto 0);
              CLK, LOAD : in STD_LOGIC;
              carry : inout STD_LOGIC_VECTOR(4 downto 0);
              minuty_U : inout STD_LOGIC
              );

end multiplekser;

architecture Behavioral of multiplekser is

signal REFRESH_S0 : STD_LOGIC;

signal WEJSCIE_DEKODERA : STD_LOGIC_VECTOR(3 downto 0);

signal POZ_L : STD_LOGIC_VECTOR(1 downto 0);
signal DEKODER_VAL : STD_LOGIC_VECTOR(3 downto 0);
signal MINUTES_J_ENABLE : STD_LOGIC;
signal MINUTES_J : STD_LOGIC_VECTOR(3 downto 0);
signal MINUTES_D_ENABLE : STD_LOGIC;
signal MINUTES_D : STD_LOGIC_VECTOR(3 downto 0);

signal HOUR_J_ENABLE : STD_LOGIC;
signal HOUR_J : STD_LOGIC_VECTOR(3 downto 0);

signal HOUR_D_ENABLE : STD_LOGIC;
signal HOUR_D : STD_LOGIC_VECTOR(3 downto 0);

    COMPONENT licznik10
    PORT(
        clock : IN std_logic;
        EN : IN std_logic;
        reset : IN std_logic;
        carry : INOUT std_logic;
        wyjscie : INOUT std_logic_vector(3 downto 0)
        );
    END COMPONENT;

    COMPONENT prescaler
    PORT(
        CLK : IN std_logic;
        LOAD : IN std_logic;
        line : inout STD_LOGIC_VECTOR(1 downto 0);
        minuty_J : inout STD_LOGIC_VECTOR(3 downto 0);
        minuty_D : inout STD_LOGIC_VECTOR(3 downto 0);
        godziny_J : inout STD_LOGIC_VECTOR(3 downto 0);
        godziny_D : inout STD_LOGIC_VECTOR(3 downto 0);
        minuty_UP : inout STD_LOGIC;
        refresh : INOUT std_logic
        );
    END COMPONENT;

    COMPONENT dekoder
    PORT(
        wejscie : IN std_logic_vector(3 downto 0);
        poz_licz : INOUT std_logic_vector(1 downto 0);
        wlacznik : INOUT std_logic_vector(3 downto 0);
        wyjscie : INOUT std_logic_vector(6 downto 0)
        );
    END COMPONENT;

begin

    Presc: prescaler PORT MAP(
        refresh => REFRESH_S0,
        line => POZ_L,
        minuty_J => MINUTES_J,
        minuty_D => MINUTES_D,
        godziny_J => HOUR_J,
        godziny_D => HOUR_D,
        minuty_UP => minuty_U,
        CLK => CLK,
        LOAD => LOAD
    );

    with POZ_L select
        WEJSCIE_DEKODERA <=     MINUTES_J when "00",
                                    MINUTES_D when "01",
                                    HOUR_J when "10",
                                    HOUR_D when "11",
                                    MINUTES_J when others;

        dekod: dekoder PORT MAP(
        poz_licz => POZ_L,
        wlacznik => segLine,
        wejscie => WEJSCIE_DEKODERA,
        wyjscie => segCode(7 downto 1)
    );

    with POZ_L select
        segCode(0) <=   REFRESH_S0 when "00",
                            '1' when others;

end Behavioral;