WrapperTestBench

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity WrapperTestBench is
end WrapperTestBench;

architecture Behavioral of WrapperTestBench is
   -- Conponent Declaration
   Component Wrapper
   Port (   FROM_STACK, FROM_IMMED : in    STD_LOGIC_VECTOR(9 downto 0);
                           MUX_SEL : in    STD_LOGIC_VECTOR(1 downto 0);
           PC_LD, PC_INC, RST, clk : in    STD_LOGIC;
                  PC_COUNT_MONITOR : out   STD_LOGIC_VECTOR(9 downto 0);    -- Used for debugging
                                IR : out   STD_LOGIC_VECTOR(17 downto 0));
   end Component;

   -- Inputs
   signal FROM_STACK_tb :   STD_LOGIC_VECTOR(9 downto 0) := "0011001100"; --x0CC
   signal FROM_IMMED_tb :   STD_LOGIC_VECTOR(9 downto 0) := "0110101010"; --x1AA
   signal MUX_SEL_tb    :   STD_LOGIC_VECTOR(1 downto 0) := (others => '0');
   signal PC_LD_tb      :   STD_LOGIC := '0';
   signal PC_INC_tb     :   STD_LOGIC := '0';
   signal RST_tb        :   STD_LOGIC := '0';
   signal clk_tb        :   STD_LOGIC := '0';

   -- Outputs
   signal PC_COUNT_MONITOR_tb   :   STD_LOGIC_VECTOR(9 downto 0);
   signal               IR_tb   :   STD_LOGIC_VECTOR(17 downto 0);

   -- Clock period definitions
   constant CLK_period  : time := 10 ns;

begin

    -- Instantiate SUT
    SUT: Wrapper port map(
            FROM_STACK  =>  FROM_STACK_tb,
            FROM_IMMED  =>  FROM_IMMED_tb,
            MUX_SEL     =>  MUX_SEL_tb,
            PC_LD       =>  PC_LD_tb,
            PC_INC      =>  PC_INC_tb,
            RST         =>  RST_tb,
            clk         =>  clk_tb,
            PC_COUNT_MONITOR    =>  PC_COUNT_MONITOR_tb,
            IR          =>  IR_tb);

    -- Clock process definition
    CLK_process: process
    begin
        clk_tb <= '0';      -- Using clk_tb NOT clk!!!
        wait for CLK_period / 2;
        clk_tb <= '1';
        wait for CLK_period / 2;
    end process;

    -- Simulate process
    stim_proc: process
    begin
--      Simulation 1:
--          test PC functions are sync

        MUX_SEL_tb <= "00"; -- select input one from mux
        PC_LD_tb <= '1'; -- load in FROM_IMMED
        PC_INC_tb <= '1';
        wait for 20 ns;
        PC_LD_tb <= '0'; -- stop loading
        wait for 10 ns;
        RST_tb <= '1'; -- turn on reset
        wait for 5 ns;
        RST_tb <= '0'; -- turn off reset. the PC should NOT have reset
        wait for 25 ns;
        RST_tb <= '1'; -- reset. the PC should actually reset now
        wait for 10 ns;

--      Simulation 2:
--          test MUX selectors

        RST_tb <= '0'; -- each of the mux signals is selected to check PC output
        PC_LD_tb <= '1';
        MUX_SEL_tb <= "00";
        wait for 40 ns;
        MUX_SEL_tb <= "01";
        wait for 40 ns;
        MUX_SEL_tb <= "10";
        wait for 40 ns;


--      Simulation 3
--          test incrimenting

        PC_LD_tb <= '0';
        RST_tb <= '1'; -- reset to zero
        PC_INC_tb <= '0';
        wait for 40 ns; -- the PC will increment for 100 ns
        RST_tb <= '0';
        PC_INC_tb <= '1';
        wait for 100 ns;

--      Simulation 4
--          test IR outputs

        MUX_SEL_tb <= "00";
        FROM_IMMED_tb <= "0000010000"; -- should be line 10
        PC_LD_tb <= '1'; -- load in 10
        PC_INC_tb <= '0';
        wait for 20 ns;
        PC_LD_tb <= '0'; -- start incrimenting to see the commands in IR
        PC_INC_tb <= '1';

    end process;

end Behavioral;