LucaSkywalker

SevenCounter_tl.vhd

Nov 21st, 2020
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  1. library IEEE;
  2. use IEEE.std_logic_1164.all;
  3. use IEEE.std_logic_arith.all;
  4. use IEEE.std_logic_misc.all;
  5. use IEEE.std_logic_unsigned.all;
  6.  
  7. entity SevenCounter_tl is
  8.     port (Carry: OUT STD_LOGIC;
  9.             Output: OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
  10. end SevenCounter_tl;
  11.  
  12. architecture SevenCounter_tl_arch of SevenCounter_tl is
  13.  
  14.     component DisplayDriver
  15.         port (Data_in: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
  16.                 Output_out: OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
  17.     end component;
  18.    
  19.     component Counter
  20.         port (Clk_in: IN STD_LOGIC;
  21.                 async_rst: IN STD_LOGIC;
  22.                 pData_in: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
  23.                 pData_en_in: IN STD_LOGIC;
  24.                 BCD_mode_in: IN STD_LOGIC;
  25.                 CNTR_en_in: IN STD_LOGIC;
  26.                 CNTR_out: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
  27.                 Carry_out: OUT STD_LOGIC);
  28.     end component;
  29.    
  30.     component SevenCounter_tb
  31.         port (Clk_out : OUT STD_LOGIC;
  32.                 rst_out: OUT STD_LOGIC;
  33.                 pData_out: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
  34.                 pData_en_out: OUT STD_LOGIC;
  35.                 BCD_mode_out: OUT STD_LOGIC;
  36.                 CNTR_en_out: OUT STD_LOGIC);
  37.     end component;
  38.    
  39.     signal Data : STD_LOGIC_VECTOR(3 DOWNTO 0);
  40.     signal Clk : STD_LOGIC;
  41.     signal rst : STD_LOGIC;
  42.     signal pData : STD_LOGIC_VECTOR(3 DOWNTO 0);
  43.     signal pData_en : STD_LOGIC;
  44.     signal BCD_mode : STD_LOGIC;
  45.     signal CNTR_en : STD_LOGIC;
  46.    
  47.         begin
  48.         Driver_1 : DisplayDriver port map ( Data_in => Data,
  49.                             Output_out => Output);
  50.                                                        
  51.         counter_1 : counter port map (      Clk_in => Clk,
  52.                             async_rst => rst,
  53.                             pData_in => pData,
  54.                             pData_en_in => pData_en,
  55.                             BCD_mode_in => BCD_mode,
  56.                             CNTR_en_in => CNTR_en,
  57.                             CNTR_out => Data,
  58.                             Carry_out => Carry);
  59.                                                        
  60.         tb_1 : SevenCounter_tb port map (   Clk_out => Clk,
  61.                             rst_out => rst,
  62.                             pData_out => pData,
  63.                             pData_en_out => pData_en,
  64.                             BCD_mode_out => BCD_mode,
  65.                             CNTR_en_out => CNTR_en);
  66. end SevenCounter_tl_arch;
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