library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity z1 is
port(
    iCLK : in std_logic;
    inRST : in std_logic;
    iLOAD : in std_logic;
    iD : in std_logic_vector(7 downto 0);
    oONES : out std_logic_vector(7 downto 0);
    oEVEN : out std_logic_vector(2 downto 0);
    oODD : out std_logic_vector(2 downto 0)
    );
end entity;

architecture bod of z1 is
    signal sREG : std_logic_vector(7 downto 0);
    signal sCOPY : std_logic_vector(7 downto 0);
    signal sBRJ : std_logic_vector(7 downto 0);
    signal sPAR : std_logic_vector(2 downto 0);
    signal sNEPAR : std_logic_vector(2 downto 0);
    signal sSTOP : std_logic;

begin

    process(iCLK, inRST) begin ---------------------- pravi reg i broji jedinice
        if(inRST = '0') then
            sREG <= (others => '0');
            sBRJ <= (others => '0');
        elsif(rising_edge(iCLK)) then
            if(iLOAD = '1') then
                sREG <= sREG(6 downto 0) & sCOPY(7);
                sCOPY <= sCOPY(6 downto 0) & '0';
            else
                sCOPY <= iD;
                if(sREG(0) = '1') then
                    sBRJ <= sBRJ + 1;
                end if;
                sREG <= '0' & sREG(7 downto 1);
            end if;
        end if;
    end process;

    process(icLK, inRST) begin ---------------------- broji par i nepar
        if(inRST = '0') then
            sPAR <= (others => '0');
            sNEPAR <= (others => '0');
            sSTOP <= '0';
        elsif(rising_edge(iCLK)) then
            if(iLOAD = '1') then
                if(sSTOP = '0') then
                    if(iD(0) = '0') then
                        sPAR <= sPAR + 1;
                        sSTOP <= '1';
                    else
                        sNEPAR <= sNEPAR + 1;
                        sSTOP <= '1';
                    end if;
                end if;
            else
                sSTOP <= '0';
            end if;
        end if;
    end process;



    oONES <= sBRJ;
    oEVEN <= sPAR;
    oODD <= sNEPAR;

end architecture;