library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity FP_design is
    PORT(
        aclk: in std_logic;
        a_data: in std_logic_vector(31 downto 0);
        a_data_valid: in std_logic;
        b_data: in std_logic_vector(31 downto 0);
        b_data_valid: in std_logic;
        sum_data: out std_logic_vector(31 downto 0);
        sum_data_valid: out std_logic
    );
end FP_design;

architecture Behavioral of FP_design is
    COMPONENT floating_point_0 --add/sub
        PORT (
            aclk : IN STD_LOGIC;
            s_axis_a_tvalid : IN STD_LOGIC;
            s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
            s_axis_b_tvalid : IN STD_LOGIC;
            s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
            s_axis_operation_tvalid : IN STD_LOGIC;
            s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
            m_axis_result_tvalid : OUT STD_LOGIC;
            m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
        );
    END COMPONENT;

    signal sub_data: std_logic_vector(31 downto 0);
    signal sub_valid: std_logic;
begin
    fp0: floating_point_0 port map(
        aclk => aclk,
        s_axis_a_tvalid => a_data_valid,
        s_axis_a_tdata => a_data,
        s_axis_b_tvalid => b_data_valid,
        s_axis_b_tdata => b_data,
        s_axis_operation_tvalid => '1',
        s_axis_operation_tdata => "00000001", --sub
        m_axis_result_tvalid => sub_valid,
        m_axis_result_tdata => sub_data
    );

    fp1: floating_point_0 port map(
        aclk => aclk,
        s_axis_a_tvalid => sub_valid,
        s_axis_a_tdata => sub_data,
        s_axis_b_tvalid => sub_valid,
        s_axis_b_tdata => "00111111100000000000000000000000",  --1
        s_axis_operation_tvalid => '1',
        s_axis_operation_tdata => "00000000", --add
        m_axis_result_tvalid => sum_data_valid,
        m_axis_result_tdata => sum_data
    );

end Behavioral;