testvhdl

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity vhdl_test is
    port(
    a,b:        in std_logic;
    in1, in2:   out std_logic;
    y_and:      out std_logic;
    y_or:       out std_logic;
    y_xor:      out std_logic
    );
end vhdl_test;

architecture arch1 of vhdl_test is
begin
     in1 <= a;
     in2 <= b;

     y_and <= not ((not a) and (not b));
     y_or  <= not ((not a) or (not b));
     y_xor <= not ((not a) xor (not b));
end arch1;