[VHDL] D Flip-flop Asynchronous Preset // Behavioral

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-- Company:
-- Engineer:
--
-- Create Date:    21:30:35 04/01/2017
-- Design Name:
-- Module Name:    D_FF_ASYNC_PRESET_BEH - Behavioral

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity D_FF_ASYNC_PRESET_BEH is
    PORT(
        CLK:        IN std_logic;   -- ulazni port dozvole upisa
        D:      IN std_logic;   -- asinhroni preset ulaz
        PRESET:     IN std_logic;   -- ulazni port podataka
        Q:          OUT std_logic   -- izlazni port podataka 1
    );
end entity D_FF_ASYNC_PRESET_BEH;

architecture Behavioral of D_FF_ASYNC_PRESET_BEH is
begin
    D_FF: process(CLK, PRESET) is
    begin
        if(PRESET = '1') then
            Q <= '1';
        else
            if (CLK'EVENT and CLK = '1') then
                Q <= D;
            end if;
        end if;
    end process;

end Behavioral;