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-- Company:
-- Engineer:
--
-- Create Date:    20:31:22 07/07/2012
-- Design Name:
-- Module Name:    filtre - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;

use work.filter_pkg.all;


entity filtre is

    port(reset_n : in std_logic;
          clk   : in std_logic;
          btn   : in std_logic;
          p_val : in std_logic;
          q_val : in std_logic;
          idata : in std_logic_vector(max_msg_bits-1 downto 0);
          leds  : out std_logic_vector(7 downto 0)
          );

end filtre;

architecture Behavioral of filtre is

signal ram : std_logic_vector(2**num_hash_bits-1 downto 0);
signal match : std_logic;

-- ran_sig
signal ran_sig : hash_array;

-- H3 signals
signal h3_data_in : std_logic_vector(max_msg_bits-1 downto 0);
signal h3_data_out : hash_o_array;

-- lfsr signals

signal lfsr_rdv : std_logic_vector (num_hash_bits-1 downto 0);

-- H3 component declaration
component h3
generic ( index : integer;
            rnd_v : hash_array
            );
port (
      data_in  : in std_logic_vector(max_msg_bits-1 downto 0);
        data_out : out std_logic_vector(num_hash_bits-1 downto 0)
        );

end component;

-- lfsr component declaration

component lfsr
    generic (random_num_length : integer);
    port (
          clk : in std_logic;
          random_num : out std_logic_vector (num_hash_bits-1 downto 0)   --output vector
        );
end component;

begin

--process(btn)
--begin
--if (btn= '1') then
--  leds <= ram(7 downto 0);
--else
--  leds <= ram (15 downto 8);
--end if;
--end process;

--leds <= "0000" & h3_data_out;
leds <= "0000000" & match;
h3_data_in <= x"00" & idata(7 downto 0);

-- H3 instantiation
h_func: for i in 0 to num_hash_functions-1 generate

 h3_inst : h3
    generic map(
            index => i,
            rnd_v => ran_sig
            )
port map(
    data_in => h3_data_in,
    data_out => h3_data_out(i));

end generate h_func;

-- lfsr instantiation
lfsr_inst : lfsr
    generic map (
            random_num_length => num_hash_bits
                    )
    port map (
            clk => clk,
            random_num => lfsr_rdv
            );



process (clk, reset_n)
variable match_int :std_logic;
begin
if reset_n = '0' then
    ram <= (others => '0');
    match <= '0';

elsif rising_edge(clk) then
   for k in 0 to num_hash_functions-1 loop
        for  b in 0 to  max_msg_length-1 loop  -- loop on the 8 bits of input byte
            for  i in 0 to  7 loop  -- loop on the 8 bits of input byte
                ran_sig(k)(b)(i) <=  lfsr_rdv ;
            end loop ;
        end loop;
    end loop;
    if (p_val ='1') then
        for i in 0 to num_hash_functions-1 loop
            ram(to_integer(unsigned(h3_data_out(i)))) <= '1';
        end loop;

    elsif (q_val ='1') then
        match_int := '1';
        for i in 0 to num_hash_functions-1 loop
            match_int := match_int and ram(to_integer(unsigned(h3_data_out(i))));
        end loop;
        match <= match_int;
    end if;

end if;
end process;

end Behavioral;