LIBRARY IEEE;
USE work.CLOCKS.all;   -- Entity that uses CLOCKS
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_textio.all;
USE std.textio.all;
USE work.txt_util.all;

ENTITY TB_FAMAKIN_XOR_CASCADES IS
END;

ARCHITECTURE TESTBENCH OF TB_FAMAKIN_XOR_CASCADES IS


---------------------------------------------------------------
-- COMPONENTS
---------------------------------------------------------------

COMPONENT famakin_xor_cascades          -- In/out Ports
    PORT(   --Clk: IN STD_LOGIC;
        OP_A: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
        OP_Q: OUT STD_LOGIC);
END COMPONENT;

COMPONENT CLOCK
    port(CLK: out std_logic);
END COMPONENT;

---------------------------------------------------------------
-- Read/Write FILES
---------------------------------------------------------------


FILE in_file : TEXT open read_mode is   "FAMAKIN_XOR_INPUT.txt";   -- Inputs, reset, enr,enl
FILE exo_file : TEXT open read_mode is  "FAMAKIN_XOR_EXP_CASCADE_OUTPUT.txt";   -- Expected output (binary)
FILE out_file : TEXT open  write_mode is  "FAMAKIN_ODDPD_Book_dataout.txt";
FILE xout_file : TEXT open  write_mode is "FAMAKIN_ODDPD_Book_TestOut.txt";
FILE hex_out_file : TEXT open  write_mode is "FAMAKIN_ODDPD_Book_hex_out.txt";

---------------------------------------------------------------
-- SIGNALS
---------------------------------------------------------------

  SIGNAL OP_A: STD_LOGIC_VECTOR(7 downto 0):= "XXXXXXXX";
  SIGNAL CLK: STD_LOGIC;
  SIGNAL OP_Q : STD_LOGIC:= 'X';
  SIGNAL Exp_Op_Q : STD_LOGIC:= 'X';
  SIGNAL Test_Out_Q : STD_LOGIC:= 'X';
  SIGNAL LineNumber: integer:=0;

---------------------------------------------------------------
-- BEGIN
---------------------------------------------------------------

BEGIN

---------------------------------------------------------------
-- Instantiate Components
---------------------------------------------------------------


U0: CLOCK port map (CLK );
Instfamakin_xor_cascades: famakin_xor_cascades port map (OP_A, OP_Q);

---------------------------------------------------------------
-- PROCESS
---------------------------------------------------------------
PROCESS

variable in_line, exo_line, out_line, xout_line : LINE;
variable comment, xcomment : string(1 to 128);
variable i : integer range 1 to 128;
variable simcomplete : boolean;

variable vOp_A   : std_logic_vector(7 downto 0):= (OTHERS => 'X');
variable vOp_Q : std_logic:= '0';
variable vExp_Op_Q : std_logic:= '0';
variable vTest_Out_Q : std_logic := '0';
variable vlinenumber: integer;

BEGIN

simcomplete := false;

while (not simcomplete) LOOP

    if (not endfile(in_file) ) then
        readline(in_file, in_line);
    else
        simcomplete := true;
    end if;

    if (not endfile(exo_file) ) then
        readline(exo_file, exo_line);
    else
        simcomplete := true;
    end if;

    if (in_line(1) = '-') then  --Skip comments
        next;
    elsif (in_line(1) = '.')  then  --exit Loop
      Test_Out_Q <= 'Z';
        simcomplete := true;
    elsif (in_line(1) = '#') then        --Echo comments to out.txt
      i := 1;
      while in_line(i) /= '.' LOOP
        comment(i) := in_line(i);
        i := i + 1;
      end LOOP;

    elsif (exo_line(1) = '-') then  --Skip comments
        next;
    elsif (exo_line(1) = '.')  then  --exit Loop
          Test_Out_Q  <= 'Z';
           simcomplete := true;
    elsif (exo_line(1) = '#') then        --Echo comments to out.txt
         i := 1;
       while exo_line(i) /= '.' LOOP
         xcomment(i) := exo_line(i);
         i := i + 1;
       end LOOP;


      write(out_line, comment);
      writeline(out_file, out_line);

      write(xout_line, xcomment);
      writeline(xout_file, xout_line);


    ELSE      --Begin processing


        read(in_line, vOp_A );
        OP_A  <= vOp_A;

        read(exo_line, vexp_Op_Q );
        read(exo_line, vTest_Out_Q );

    vlinenumber :=LineNumber;

    write(out_line, vlinenumber);
    write(out_line, STRING'("."));
    write(out_line, STRING'("    "));



    CYCLE(1,CLK);

    Exp_Op_Q      <= vexp_Op_Q;


    if (Exp_Op_Q = OP_Q) then
      Test_Out_Q <= '0';
    else
      Test_Out_Q <= 'X';
    end if;

        vOp_Q   := OP_Q;
        vTest_Out_Q:= Test_Out_Q;

        write(out_line, vOp_Q, left, 32);
        write(out_line, STRING'("       "));                           --ht is ascii for horizontal tab
        write(out_line,vTest_Out_Q, left, 5);                           --ht is ascii for horizontal tab
        write(out_line, STRING'("       "));                           --ht is ascii for horizontal tab
        write(out_line, vexp_Op_Q, left, 32);
        write(out_line, STRING'("       "));                           --ht is ascii for horizontal tab
        writeline(out_file, out_line);
        print(xout_file,    str(LineNumber)& "." & "    " &    str(OP_Q) & "          " &   str(Exp_Op_Q)  & "          " & str(Test_Out_Q) );

    END IF;
    LineNumber<= LineNumber+1;

    END LOOP;
    WAIT;

    END PROCESS;

END TESTBENCH;



CONFIGURATION cfg_TB_FAMAKIN_XOR_CASCADES OF TB_FAMAKIN_XOR_CASCADES IS
    FOR TESTBENCH
        FOR Instfamakin_xor_cascades: famakin_xor_cascades
            use entity work.famakin_xor_cascades(tree_arch);
        END FOR;
    END FOR;
END;