LucaSkywalker

IntMult_tl.vhd

Nov 28th, 2020
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  1. library IEEE;
  2. use IEEE.std_logic_1164.all;
  3. use IEEE.std_logic_arith.all;
  4. use IEEE.std_logic_misc.all;
  5. use IEEE.std_logic_unsigned.all;
  6.  
  7. entity IntMult_tl is
  8.     port (mult_result: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
  9.             mult_ready: OUT STD_LOGIC);
  10. end IntMult_tl;
  11.  
  12. architecture IntMult_tl_arch of IntMult_tl is
  13.  
  14.     component IntMult
  15.         port (Clk_in: IN STD_LOGIC;
  16.                 async_rst: IN STD_LOGIC;
  17.                 mult_start_in: IN STD_LOGIC;
  18.                 multiplicand_in: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
  19.                 multiplier_in: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
  20.                 mult_result_out: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
  21.                 mult_ready_out: OUT STD_LOGIC);
  22.     end component;
  23.    
  24.     component IntMult_tb
  25.         port (Clk_out : OUT STD_LOGIC;
  26.                 rst_out: OUT STD_LOGIC;
  27.                 mult_start_out: OUT STD_LOGIC;
  28.                 multiplicand_out: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
  29.                 multiplier_out: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
  30.     end component;
  31.    
  32.     signal Clk : STD_LOGIC;
  33.     signal rst : STD_LOGIC;
  34.     signal mult_start : STD_LOGIC;
  35.     signal multiplicand : STD_LOGIC_VECTOR(3 DOWNTO 0);
  36.     signal multiplier : STD_LOGIC_VECTOR(3 DOWNTO 0);
  37.    
  38.         begin
  39.                                                        
  40.         IntMult_1 : IntMult port map (      Clk_in => Clk,
  41.                                                         async_rst => rst,
  42.                                                         mult_start_in => mult_start,
  43.                                                         multiplicand_in => multiplicand,
  44.                                                         multiplier_in => multiplier,
  45.                                                         mult_result_out => mult_result,
  46.                                                         mult_ready_out => mult_ready);
  47.                                                        
  48.         IntMult_tb1 : IntMult_tb port map ( Clk_out => Clk,
  49.                                                         rst_out => rst,
  50.                                                         mult_start_out => mult_start,
  51.                                                         multiplicand_out => multiplicand,
  52.                                                         multiplier_out => multiplier);
  53. end IntMult_tl_arch;
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