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CSE3215_Exam.c

Apr 11th, 2012
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  1. #define BUF_SIZE    8
  2.  
  3. extern volatile char buffer[BUF_SIZE];
  4. extern volatile int index = 0;
  5.  
  6. #pragma CODE_SEG __NEAR_SEG NON_BANKED
  7. interrupt void RTI_ISR(void) {
  8.   absoluteTime++;
  9.   /* clear RTIF bit */
  10.   CRGFLG = 0x80;  
  11. }
  12.  
  13. #pragma CODE_SEG __NEAR_SEG NON_BANKED
  14. interrupt void TOF_ISR(void) {
  15.     PORTA = PORTA+1;
  16.     TFLG2 = 0x80;
  17. }
  18.  
  19. #pragma CODE_SEG __NEAR_SEG NON_BANKED
  20. interrupt void SCI0R_ISR(void) {
  21.    
  22.     if(index > 8)
  23.         index = 0;
  24.     buffer[index++] = SCI1DRL; /*Read from register*/
  25. }
  26.  
  27. #pragma CODE_SEG __NEAR_SEG NON_BANKED
  28. interrupt void OC2_ISR(void) {
  29.     TC2 = TC2 + 15000/2 /*Half period*/;
  30.     TFLG1 = 0x04; /*Clear interrupt flag*/
  31. }
  32.  
  33. interrupt void IC1_ISR(void) {
  34.     time = TC2;
  35.     TFLG1 = 0x02; /*Clear interrupt flag*/
  36. }
  37.  
  38.  
  39. #pragma CODE_SEG DEFAULT
  40. static void RTIInit(void) {
  41.   /* setup of the RTI interrupt frequency */
  42.   /* adjusted to get 1 millisecond (1.024 ms) with 16 MHz oscillator */
  43.   RTICTL = 0x1F; /* set RTI prescaler */  
  44.   CRGINT = 0x80; /* enable RTI interrupts */
  45. }
  46.  
  47. static void TimerInit(void){
  48.    
  49.     /* 10ms*(24000000/16) = 15000 */
  50.     DDRA = 0xFF; /* PORTA output*/
  51.     TSCR1 = 0x80; /* Turn on timer*/
  52.     TSRC2 = 0x85; /*Enable timer overflow, set prescalar */
  53.     TFLG2 = 0x80; /*Clear timer interrupt flag*/
  54. }
  55.  
  56. static void PWMInit(void){
  57.     PWMCTL = 0x00;  /* 8-bit Mode */
  58.     PWMPOL = 0xFF;  /* High polarity mode */
  59.     PWMCAE = 0x00;  /* Left-Aligned */
  60.     PWMPRCLK = PWMPRCLK & ~0x07;  /* PCKA = 0 */
  61.     PWMCLK = PWMCLK | 0x01;  /* PCLK0 = 1 */
  62.     PWMSCLA = 30;
  63.     PWMPER0 = 200; /*Total period of duty cycle*/
  64.     PWME = PWME | 0x01;  /* Enable PWM Channel 0 */
  65.     PWDTY0 = 120;  /* 60% duty cycle on Channel 0(120/PWMPER0) */
  66. }
  67.  
  68. static void SPI0_Init(void){
  69.     // SPI communication initialization as a master
  70.     SPI0BR  = 0b00100101;    // Baud rate = 24MHz/16 = 1.5MHz 0x53;
  71.     SPI0CR2 = 0b00010000;  // SPI0CR2_SPISWAI=1 : Stop SPI clocks when in wait mode
  72.     SPI0CR1 = 0b01010010;  // Enable SPI ; Master mode ; CPHA = 1 ;
  73.  
  74.     WOMS = 0;
  75. }
  76.  
  77. static void SCI0_Init(void){
  78.     SCI1BDL = 156; /* Set BAUD rate to 9,600 */
  79.     SCI1BDH = 0;
  80.    
  81.     SCI1CR1 = 0x00;
  82.     SCI1CR2 = 0x36; /*Recieve Interrupts, Transmit, Recieve enable */
  83. }
  84.  
  85. static void OC2_Init(void){
  86.     TSCR1 = 0x80; /*Enable Timers */
  87.     TSCR2 = 0x04; /*Set prescale to 16(0.666us) */
  88.     TIOS = 0x04; /* Set IOS2 as Output Compare*/
  89.     TCTL2 = 0x10; /*Toggle on compare*/
  90.     TFLG1 = 0x04; /*Clear OC2 flag*/
  91.     TIE = 0x04; /*Enable OC2 interupts*/   
  92. }
  93.  
  94. static void IC1_Init(void){
  95.     TSCR1 = 0x80; /* Turn on timer subsystem */
  96.     TSCR2 = 0x05; /* Set prescaler for divide by 32 */
  97.     /* 87.38 ms overflow time */
  98.     TIOS = TIOS & ~0x02; /*only IC1 is low for input */
  99.     TCTL4 = 0x04 /*EDG1A enabled, captures rising edge*/
  100.     TFGL1 = 0x02 /*Clear flag 1*/
  101. }
  102.  
  103. static void ADTD0_Init(void){
  104.     ATD0CTL2 = 0x80; /* Power up A/D, no interrupts */
  105.     ATD0CTL3 = 0x00; /* Doe eight conversions */
  106.     ATD0CTL4 = 0x85; /* 8-bit mode */
  107.     ATD0CTL5 = 0xA4; /* Cont conversion, right justified */
  108.     adcvalue = ATD0DR0H; /* Grab the value from register*/
  109. }
  110.  
  111. void SCI0_OutChar(char data) {
  112.    
  113.     while((SCI0SR1 & TDRE) == 0){};
  114.     SCI0DRL = data;
  115. }
  116.  
  117. char SCI0_InChar(void){
  118.     /* Only used when Recieve Interrupt disabled*/
  119.     while((SCI0SR1 & RDRF) == 0){};
  120.     return(SCI0DRL);
  121. }
  122.  
  123. char SCI0_ReadBuffer(void){
  124.     char data = buffer[index--];
  125.     if(index < 0)
  126.         index = 0;
  127.     return data;
  128. }
  129.  
  130. static void SPI0_send(char x){
  131.     // Send a byte to the slave blocking(CPU will wait)
  132.     while( SPI0SR_SPTEF == 0); // Wait until SPIDR becomes empty.
  133.     SPI0DR = 0xAA;              //  Clear the flag SPI0SR_STEF
  134.  
  135.     while( SPI0SR_SPIF == 0 );   // Wait until the end of an SPI transfer.  
  136.     data = SPI0DR;
  137. }
  138.  
  139. char SPI0_receive(void) {
  140.     // Receive a byte from the slave
  141.     while(SPI0SR_SPTEF == 0);  // Wait until the SPI0DR is empty
  142.     SPI0DR = 0x00;                         // Read SPI0DR to clear the SPI0SR_SPTEF flag
  143.     while(SPI0SR_SPIF == 0);      // Wait until a SPI transfer is finished  
  144.     return SPI0DR;                         // Write the received data to data    
  145. }
  146.  
  147.  
  148.  void main(void)
  149.   RTIInit();
  150.   TimerInit();
  151.   PWMInit();
  152.   SPI0_Init();
  153.   EnableInterrupts;
  154.  
  155.   SPI0_send('a');
  156.  
  157.   for(;;)
  158.   {
  159.      
  160.   }
  161.  
  162. /* Interrupt Vector Table
  163.  * const IsrFunc _vectab[] @0x3e00 /*0xFF80 =
  164. {
  165.   (IC1_ISR)0,
  166.   (OC2_ISR)0,                                        
  167.   (RTI_ISR)0,                          
  168.   (TOF_ISR)0,                          
  169.   (SCI0R_ISR)0,                                      
  170. */
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