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  1. /*
  2.  * File:   Main.c
  3.  * Author:
  4.  *
  5.  * Created on June 13, 2019, 2:22 PM
  6.  */
  7.  
  8. #define _XTAL_FREQ 32000000
  9.  
  10. // PIC16F18875 Configuration Bit Settings
  11.  
  12. // 'C' source line config statements
  13.  
  14. // CONFIG1
  15. #pragma config FEXTOSC = OFF      // External Oscillator mode selection bits (EC above 8MHz; PFM set to high power)
  16. #pragma config RSTOSC = HFINT32  // Power-up default value for COSC bits (EXTOSC operating per FEXTOSC bits)
  17. #pragma config CLKOUTEN = OFF    // Clock Out Enable bit (CLKOUT function is disabled; i/o or oscillator function on OSC2)
  18. #pragma config CSWEN = ON        // Clock Switch Enable bit (Writing to NOSC and NDIV is allowed)
  19. #pragma config FCMEN = ON        // Fail-Safe Clock Monitor Enable bit (FSCM timer enabled)
  20.  
  21. // CONFIG2
  22. #pragma config MCLRE = ON        // Master Clear Enable bit (MCLR pin is Master Clear function)
  23. #pragma config PWRTE = OFF       // Power-up Timer Enable bit (PWRT disabled)
  24. #pragma config LPBOREN = OFF     // Low-Power BOR enable bit (ULPBOR disabled)
  25. #pragma config BOREN = OFF       // Brown-out reset enable bits (Brown-out Reset Enabled, SBOREN bit is ignored)
  26. #pragma config BORV = LO         // Brown-out Reset Voltage Selection (Brown-out Reset Voltage (VBOR) set to 1.9V on LF, and 2.45V on F Devices)
  27. #pragma config ZCD = OFF         // Zero-cross detect disable (Zero-cross detect circuit is disabled at POR.)
  28. #pragma config PPS1WAY = ON      // Peripheral Pin Select one-way control (The PPSLOCK bit can be cleared and set only once in software)
  29. #pragma config STVREN = ON       // Stack Overflow/Underflow Reset Enable bit (Stack Overflow or Underflow will cause a reset)
  30.  
  31. // CONFIG3
  32. #pragma config WDTCPS = WDTCPS_31// WDT Period Select bits (Divider ratio 1:65536; software control of WDTPS)
  33. #pragma config WDTE = OFF        // WDT operating mode (WDT enabled regardless of sleep; SWDTEN ignored)
  34. #pragma config WDTCWS = WDTCWS_7 // WDT Window Select bits (window always open (100%); software control; keyed access not required)
  35. #pragma config WDTCCS = SC       // WDT input clock selector (Software Control)
  36.  
  37. // CONFIG4
  38. #pragma config WRT = OFF         // UserNVM self-write protection bits (Write protection off)
  39. #pragma config SCANE = available // Scanner Enable bit (Scanner module is available for use)
  40. #pragma config LVP = OFF          // Low Voltage Programming Enable bit (Low Voltage programming enabled. MCLR/Vpp pin function is MCLR.)
  41.  
  42. // CONFIG5
  43. #pragma config CP = OFF          // UserNVM Program memory code protection bit (Program Memory code protection disabled)
  44. #pragma config CPD = OFF         // DataNVM code protection bit (Data EEPROM code protection disabled)
  45.  
  46. #include <xc.h>
  47.  
  48. unsigned getSPBRG(unsigned baudrate, char brg16, char brgh) {
  49.     unsigned mult;
  50.     if (brg16 == 0 && brgh == 0) mult = 64;
  51.     else if (brg16 == 1 && brgh == 1) mult = 4;
  52.     else mult = 16;
  53.    
  54.     // baudrate = fOsc / (mult*(spbrg + 1))
  55.     // baudrate * (spbrg + 1) = fOsc / mult
  56.     // spbrg + 1 = (fOsc / mult) / baudrate
  57.     // spbrg = (fOsc / mult) / baudrate - 1
  58.     return (_XTAL_FREQ / mult) / baudrate - 1;
  59. }
  60.  
  61. void main(void)
  62. {
  63.     TRISA = 0b00000000;
  64.     TRISB = 0b00000000;
  65.    
  66.     // LATA = 1; __delay_ms(1000);
  67.  
  68.     PORTC = 0;
  69.     TRISC = 0b10000000; // all outputs, except RX on RC7
  70.     ANSELC = 0b00000000; // disable analog
  71.     //init USART
  72.     // SPEN  RX9   SREN  CREN  ADDEN FERR OERR   RX9D
  73.     RCSTA = 0b10100000;        //    TX9D=0 -->8-bit; SPEN=1, CREN=1, addr-det disabled.
  74.     // CSRC  TX9   TXEN  SYNC  SENDB BRGH  TRMT  TX9D
  75.     TXSTA = 0b00100100;        //    TX9D=0 -->8-bit; BRGH=1; TXEN=1 --> enable, SYNC=0 --> async
  76.     //ABDOVF RCIDL NOP   SCKP  BRG16 NOP   WUE   ABDEN
  77.     BAUDCON = 0b00001000;    //    SCKP=0 -> not inverted, BRG16=1, WUE=0, ABDEN=0
  78.    
  79.     // LATA = 2; __delay_ms(1000);
  80.  
  81.     unsigned brg = getSPBRG(4800, 1, 1);
  82.     SPBRGL = brg & 0xFF;
  83.     SPBRGH = brg >> 8;
  84.  
  85.    
  86.     // LATA = 3; __delay_ms(1000);
  87.  
  88.     while(1){
  89.         TXREG = 'X';
  90.         while (!TRMT);
  91.         TXREG = '\n';
  92.         while (!TRMT);
  93.         __delay_ms(500);
  94.         LATA = 4; __delay_ms(1000);
  95.     }
  96.    
  97.     LATA = 7;
  98.     return;
  99. }
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