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Jan 31st, 2014
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  1. entity vga_sdram is
  2.     generic (
  3.         -- VGA Info
  4.         HD : integer := 640; -- Horizontal display area
  5.         HF : integer := 16; -- Horizontal front porch
  6.         HB : integer := 48; -- Horizontal back porch
  7.         HR : integer := 96; -- Horizontal retrace
  8.         VD : integer := 480; -- Vertical display area
  9.         VF : integer := 10; -- Vertical front porch
  10.         VB : integer := 31; -- Vertical back porch
  11.         VR : integer := 2; -- Vertical retrace
  12.  
  13.         -- bits per pixels
  14.         RED_WIDTH : integer := 4;
  15.         GREEN_WIDTH : integer := 4;
  16.         BLUE_WIDTH : integer := 4;
  17.  
  18.         ADDR_WIDTH : integer := 22;
  19.         DATA_WIDTH : integer := 16;
  20.         BUF_WIDTH : integer := 12
  21.     );
  22.     port (
  23.         clock : in std_logic;
  24.         reset : in std_logic;
  25.  
  26.         -- VGA interface
  27.         hsync : out std_logic;
  28.         vsync : out std_logic;
  29.         red : out std_logic_vector(RED_WIDTH - 1 downto 0);
  30.         green : out std_logic_vector(GREEN_WIDTH - 1 downto 0);
  31.         blue : out std_logic_vector(BLUE_WIDTH - 1 downto 0);
  32.  
  33.         -- sdram interface
  34.         mem_busy : in std_logic;
  35.         mem_strobe : out std_logic;
  36.         mem_wr : out std_logic;
  37.         mem_addr : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
  38.         mem_nwords : out std_logic_vector(BUF_WIDTH - 1 downto 0);
  39.  
  40.         buf_clock : in std_logic;
  41.         buf_wr : in std_logic;
  42.         buf_addr : in std_logic_vector(BUF_WIDTH - 1 downto 0);
  43.         buf_data_i : in std_logic_vector(DATA_WIDTH - 1 downto 0);
  44.         buf_data_o : out std_logic_vector(DATA_WIDTH - 1 downto 0)
  45.     );
  46. end vga_sdram;
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